APLL NO INPUT SIGNAL COMPENSATION CIRCUIT

APLL NO INPUT SIGNAL COMPENSATION CIRCUIT

PURPOSE:To attain immediate lock-in when an input signal is intermitted and a data is restored again by providing a specific circuit holding the state of a point of time when the last data is inputted. CONSTITUTION:In the APLL circuit comprising a phase comparator 1, a voltage controlled oscillator...

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1. Verfasser: ASAKA KAZUHIKO
Format: Patent
Sprache:eng
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AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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creator ASAKA KAZUHIKO
description PURPOSE:To attain immediate lock-in when an input signal is intermitted and a data is restored again by providing a specific circuit holding the state of a point of time when the last data is inputted. CONSTITUTION:In the APLL circuit comprising a phase comparator 1, a voltage controlled oscillator 5 connected to an output of the comparator 1, and a feedback path connecting the output of the voltage controlled oscillator 5 and the one input of the phase comparator, an integration means 2 integrating the output of the phase comparator 1, an input signal detection circuit 4 detecting the presence of an input signal to the phase comparator 1, a switch 6 controlled by the input signal detection circuit 4 and a hold means 3 holding two outputs of the integration means while being connected to the output of the integration means 2 via the switch 6 are provided between the phase comparator 1 and the voltage controlled oscillator 5. Thus, when the input signal is interrupted and then restored again, the immediate lock-in is attained.
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CONSTITUTION:In the APLL circuit comprising a phase comparator 1, a voltage controlled oscillator 5 connected to an output of the comparator 1, and a feedback path connecting the output of the voltage controlled oscillator 5 and the one input of the phase comparator, an integration means 2 integrating the output of the phase comparator 1, an input signal detection circuit 4 detecting the presence of an input signal to the phase comparator 1, a switch 6 controlled by the input signal detection circuit 4 and a hold means 3 holding two outputs of the integration means while being connected to the output of the integration means 2 via the switch 6 are provided between the phase comparator 1 and the voltage controlled oscillator 5. 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CONSTITUTION:In the APLL circuit comprising a phase comparator 1, a voltage controlled oscillator 5 connected to an output of the comparator 1, and a feedback path connecting the output of the voltage controlled oscillator 5 and the one input of the phase comparator, an integration means 2 integrating the output of the phase comparator 1, an input signal detection circuit 4 detecting the presence of an input signal to the phase comparator 1, a switch 6 controlled by the input signal detection circuit 4 and a hold means 3 holding two outputs of the integration means while being connected to the output of the integration means 2 via the switch 6 are provided between the phase comparator 1 and the voltage controlled oscillator 5. Thus, when the input signal is interrupted and then restored again, the immediate lock-in is attained.</abstract><oa>free_for_read</oa></addata></record>
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subjects AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title APLL NO INPUT SIGNAL COMPENSATION CIRCUIT
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