CONTROLLING METHOD FOR INPUT/OUTPUT CONTROLLER
PURPOSE:To improve flexibility and maintenance by setting up addresses in respective IOCs based on program control at the initialization and informing necessary state information such as the kind of the IOC concerned and the state of a terminal from the IOC setting up its address to a CPU. CONSTITUT...
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creator | ITAO MINORU |
description | PURPOSE:To improve flexibility and maintenance by setting up addresses in respective IOCs based on program control at the initialization and informing necessary state information such as the kind of the IOC concerned and the state of a terminal from the IOC setting up its address to a CPU. CONSTITUTION:At the initialization, a channel 3 outputs a sense request signal, accesses the IOCs sequentially in accordance with priority and sends the address signal of a device address previously fixed in the channel 3 to a common bus 7 to set up the device address in the accessed IOC out of the IOCs 4a-4d. At the end of the address setting, the IOCs 4a-4d sends signals indicating the kinds of the devices concerned and the state information to the common bus 7. The CPU 1 receives the signals and stores them correspondingly to the device addresses. Consequently, the CPU 1 can detect the kinds and states of the IOCs corresponding to the device addresses. |
format | Patent |
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CONSTITUTION:At the initialization, a channel 3 outputs a sense request signal, accesses the IOCs sequentially in accordance with priority and sends the address signal of a device address previously fixed in the channel 3 to a common bus 7 to set up the device address in the accessed IOC out of the IOCs 4a-4d. At the end of the address setting, the IOCs 4a-4d sends signals indicating the kinds of the devices concerned and the state information to the common bus 7. The CPU 1 receives the signals and stores them correspondingly to the device addresses. Consequently, the CPU 1 can detect the kinds and states of the IOCs corresponding to the device addresses.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1987</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19871017&DB=EPODOC&CC=JP&NR=S62237555A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19871017&DB=EPODOC&CC=JP&NR=S62237555A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ITAO MINORU</creatorcontrib><title>CONTROLLING METHOD FOR INPUT/OUTPUT CONTROLLER</title><description>PURPOSE:To improve flexibility and maintenance by setting up addresses in respective IOCs based on program control at the initialization and informing necessary state information such as the kind of the IOC concerned and the state of a terminal from the IOC setting up its address to a CPU. CONSTITUTION:At the initialization, a channel 3 outputs a sense request signal, accesses the IOCs sequentially in accordance with priority and sends the address signal of a device address previously fixed in the channel 3 to a common bus 7 to set up the device address in the accessed IOC out of the IOCs 4a-4d. At the end of the address setting, the IOCs 4a-4d sends signals indicating the kinds of the devices concerned and the state information to the common bus 7. The CPU 1 receives the signals and stores them correspondingly to the device addresses. Consequently, the CPU 1 can detect the kinds and states of the IOCs corresponding to the device addresses.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1987</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNBz9vcLCfL38fH0c1fwdQ3x8HdRcPMPUvD0CwgN0fcPDQFSCjA1rkE8DKxpiTnFqbxQmptB0c01xNlDN7UgPz61uCAxOTUvtSTeKyDYzMjI2NzU1NTRmBg1ACO6Jpo</recordid><startdate>19871017</startdate><enddate>19871017</enddate><creator>ITAO MINORU</creator><scope>EVB</scope></search><sort><creationdate>19871017</creationdate><title>CONTROLLING METHOD FOR INPUT/OUTPUT CONTROLLER</title><author>ITAO MINORU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS62237555A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1987</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>ITAO MINORU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ITAO MINORU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CONTROLLING METHOD FOR INPUT/OUTPUT CONTROLLER</title><date>1987-10-17</date><risdate>1987</risdate><abstract>PURPOSE:To improve flexibility and maintenance by setting up addresses in respective IOCs based on program control at the initialization and informing necessary state information such as the kind of the IOC concerned and the state of a terminal from the IOC setting up its address to a CPU. CONSTITUTION:At the initialization, a channel 3 outputs a sense request signal, accesses the IOCs sequentially in accordance with priority and sends the address signal of a device address previously fixed in the channel 3 to a common bus 7 to set up the device address in the accessed IOC out of the IOCs 4a-4d. At the end of the address setting, the IOCs 4a-4d sends signals indicating the kinds of the devices concerned and the state information to the common bus 7. The CPU 1 receives the signals and stores them correspondingly to the device addresses. Consequently, the CPU 1 can detect the kinds and states of the IOCs corresponding to the device addresses.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | CONTROLLING METHOD FOR INPUT/OUTPUT CONTROLLER |
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