SEMICONDUCTOR LOGIC CIRCUIT DEVICE
PURPOSE:To reduce a reactive region by forming specific relationship among the number of cell lines, the sum of cell length and the sum of the cell length of latch cells, arranging latch cells to cell lines corresponding to the number of an integer closest to the relationship and disposing only non-...
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creator | MIURA CHIHEI MIYAMOTO SHUNSUKE |
description | PURPOSE:To reduce a reactive region by forming specific relationship among the number of cell lines, the sum of cell length and the sum of the cell length of latch cells, arranging latch cells to cell lines corresponding to the number of an integer closest to the relationship and disposing only non-latch cells to other cell lines. CONSTITUTION:Cell lines are constituted so that cells of the same kind are disposed to one cell line, latch cells are arranged to a cell line corresponding to the number of an integer more than and closest to mXl/L when the number of cell lines is represented by (m), the sum of cell length by L and the sum of the cell length of latch cells by (l), and only non-latch cells are disposed to other cell lines of m-m1. A device is organized of cell lines such as five ones 6-10, the latch cell 2 is arranged to cell lines such as three ones, and only the non-latch cells 3, 4 are disposed to cell lines such as two ones. The non-latch cell is disposed at the central section of the cell line 10. Accordingly, the mixed arrangement of the latch cells and the non-latch cells in the same cell lines can be prevented, thus reducing reactive regions, then minimizing chip areas. |
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CONSTITUTION:Cell lines are constituted so that cells of the same kind are disposed to one cell line, latch cells are arranged to a cell line corresponding to the number of an integer more than and closest to mXl/L when the number of cell lines is represented by (m), the sum of cell length by L and the sum of the cell length of latch cells by (l), and only non-latch cells are disposed to other cell lines of m-m1. A device is organized of cell lines such as five ones 6-10, the latch cell 2 is arranged to cell lines such as three ones, and only the non-latch cells 3, 4 are disposed to cell lines such as two ones. The non-latch cell is disposed at the central section of the cell line 10. Accordingly, the mixed arrangement of the latch cells and the non-latch cells in the same cell lines can be prevented, thus reducing reactive regions, then minimizing chip areas.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1987</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19871014&DB=EPODOC&CC=JP&NR=S62234342A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19871014&DB=EPODOC&CC=JP&NR=S62234342A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MIURA CHIHEI</creatorcontrib><creatorcontrib>MIYAMOTO SHUNSUKE</creatorcontrib><title>SEMICONDUCTOR LOGIC CIRCUIT DEVICE</title><description>PURPOSE:To reduce a reactive region by forming specific relationship among the number of cell lines, the sum of cell length and the sum of the cell length of latch cells, arranging latch cells to cell lines corresponding to the number of an integer closest to the relationship and disposing only non-latch cells to other cell lines. CONSTITUTION:Cell lines are constituted so that cells of the same kind are disposed to one cell line, latch cells are arranged to a cell line corresponding to the number of an integer more than and closest to mXl/L when the number of cell lines is represented by (m), the sum of cell length by L and the sum of the cell length of latch cells by (l), and only non-latch cells are disposed to other cell lines of m-m1. A device is organized of cell lines such as five ones 6-10, the latch cell 2 is arranged to cell lines such as three ones, and only the non-latch cells 3, 4 are disposed to cell lines such as two ones. The non-latch cell is disposed at the central section of the cell line 10. Accordingly, the mixed arrangement of the latch cells and the non-latch cells in the same cell lines can be prevented, thus reducing reactive regions, then minimizing chip areas.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1987</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAKdvX1dPb3cwl1DvEPUvDxd_d0VnD2DHIO9QxRcHEN83R25WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8V4BwWZGRsYmxiZGjsbEqAEAR9kixQ</recordid><startdate>19871014</startdate><enddate>19871014</enddate><creator>MIURA CHIHEI</creator><creator>MIYAMOTO SHUNSUKE</creator><scope>EVB</scope></search><sort><creationdate>19871014</creationdate><title>SEMICONDUCTOR LOGIC CIRCUIT DEVICE</title><author>MIURA CHIHEI ; MIYAMOTO SHUNSUKE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS62234342A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1987</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MIURA CHIHEI</creatorcontrib><creatorcontrib>MIYAMOTO SHUNSUKE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MIURA CHIHEI</au><au>MIYAMOTO SHUNSUKE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR LOGIC CIRCUIT DEVICE</title><date>1987-10-14</date><risdate>1987</risdate><abstract>PURPOSE:To reduce a reactive region by forming specific relationship among the number of cell lines, the sum of cell length and the sum of the cell length of latch cells, arranging latch cells to cell lines corresponding to the number of an integer closest to the relationship and disposing only non-latch cells to other cell lines. CONSTITUTION:Cell lines are constituted so that cells of the same kind are disposed to one cell line, latch cells are arranged to a cell line corresponding to the number of an integer more than and closest to mXl/L when the number of cell lines is represented by (m), the sum of cell length by L and the sum of the cell length of latch cells by (l), and only non-latch cells are disposed to other cell lines of m-m1. A device is organized of cell lines such as five ones 6-10, the latch cell 2 is arranged to cell lines such as three ones, and only the non-latch cells 3, 4 are disposed to cell lines such as two ones. The non-latch cell is disposed at the central section of the cell line 10. Accordingly, the mixed arrangement of the latch cells and the non-latch cells in the same cell lines can be prevented, thus reducing reactive regions, then minimizing chip areas.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR LOGIC CIRCUIT DEVICE |
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