AUTOMATIC THRESHOLD LEVEL CONTROL SYSTEM

AUTOMATIC THRESHOLD LEVEL CONTROL SYSTEM

PURPOSE:To stabilizing reading operation for input signals of respective channels by setting an optimum threshold level for each channel even when the length of a bus is long. CONSTITUTION:Automatic threshold control circuits 1 - (m) are provided corresponding to the 1st - (m)th channels. Each contr...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: AMAMIYA SHIGEO, MURANO KAZUO
Format: Patent
Sprache:eng
Schlagworte:
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
MULTIPLEX COMMUNICATION
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator AMAMIYA SHIGEO
MURANO KAZUO
description PURPOSE:To stabilizing reading operation for input signals of respective channels by setting an optimum threshold level for each channel even when the length of a bus is long. CONSTITUTION:Automatic threshold control circuits 1 - (m) are provided corresponding to the 1st - (m)th channels. Each control circuit has the same constitution of the 1st comparator 11, the 2nd comparator 12, the 1st AND gate 13, the 2nd AND gate 14, and a control circuit 15. The circuits 1 - (m) set optimum threshold levels for the respective channels with gate signals B1 GATE, B2GATE...EmGATE of the respective channels. A control circuit 25 selects an optimum threshold level and data B2 is read out by the 2nd compara tor 24 with the 2nd selected threshold levels T2.1, T2.2...T2.n, passed through an AND gate 24, and outputted as B2DATA from an output terminal 27.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPS6218847A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPS6218847A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPS6218847A3</originalsourceid><addsrcrecordid>eNrjZNBwDA3x93UM8XRWCPEIcg328PdxUfBxDXP1UXD29wsJ8vdRCI4MDnH15WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8V4BwWZGhhYWJuaOxkQoAQDtFCRf</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>AUTOMATIC THRESHOLD LEVEL CONTROL SYSTEM</title><source>esp@cenet</source><creator>AMAMIYA SHIGEO ; MURANO KAZUO</creator><creatorcontrib>AMAMIYA SHIGEO ; MURANO KAZUO</creatorcontrib><description>PURPOSE:To stabilizing reading operation for input signals of respective channels by setting an optimum threshold level for each channel even when the length of a bus is long. CONSTITUTION:Automatic threshold control circuits 1 - (m) are provided corresponding to the 1st - (m)th channels. Each control circuit has the same constitution of the 1st comparator 11, the 2nd comparator 12, the 1st AND gate 13, the 2nd AND gate 14, and a control circuit 15. The circuits 1 - (m) set optimum threshold levels for the respective channels with gate signals B1 GATE, B2GATE...EmGATE of the respective channels. A control circuit 25 selects an optimum threshold level and data B2 is read out by the 2nd compara tor 24 with the 2nd selected threshold levels T2.1, T2.2...T2.n, passed through an AND gate 24, and outputted as B2DATA from an output terminal 27.</description><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; MULTIPLEX COMMUNICATION</subject><creationdate>1987</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19870127&amp;DB=EPODOC&amp;CC=JP&amp;NR=S6218847A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19870127&amp;DB=EPODOC&amp;CC=JP&amp;NR=S6218847A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>AMAMIYA SHIGEO</creatorcontrib><creatorcontrib>MURANO KAZUO</creatorcontrib><title>AUTOMATIC THRESHOLD LEVEL CONTROL SYSTEM</title><description>PURPOSE:To stabilizing reading operation for input signals of respective channels by setting an optimum threshold level for each channel even when the length of a bus is long. CONSTITUTION:Automatic threshold control circuits 1 - (m) are provided corresponding to the 1st - (m)th channels. Each control circuit has the same constitution of the 1st comparator 11, the 2nd comparator 12, the 1st AND gate 13, the 2nd AND gate 14, and a control circuit 15. The circuits 1 - (m) set optimum threshold levels for the respective channels with gate signals B1 GATE, B2GATE...EmGATE of the respective channels. A control circuit 25 selects an optimum threshold level and data B2 is read out by the 2nd compara tor 24 with the 2nd selected threshold levels T2.1, T2.2...T2.n, passed through an AND gate 24, and outputted as B2DATA from an output terminal 27.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>MULTIPLEX COMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1987</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNBwDA3x93UM8XRWCPEIcg328PdxUfBxDXP1UXD29wsJ8vdRCI4MDnH15WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8V4BwWZGhhYWJuaOxkQoAQDtFCRf</recordid><startdate>19870127</startdate><enddate>19870127</enddate><creator>AMAMIYA SHIGEO</creator><creator>MURANO KAZUO</creator><scope>EVB</scope></search><sort><creationdate>19870127</creationdate><title>AUTOMATIC THRESHOLD LEVEL CONTROL SYSTEM</title><author>AMAMIYA SHIGEO ; MURANO KAZUO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS6218847A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1987</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>MULTIPLEX COMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>AMAMIYA SHIGEO</creatorcontrib><creatorcontrib>MURANO KAZUO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>AMAMIYA SHIGEO</au><au>MURANO KAZUO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>AUTOMATIC THRESHOLD LEVEL CONTROL SYSTEM</title><date>1987-01-27</date><risdate>1987</risdate><abstract>PURPOSE:To stabilizing reading operation for input signals of respective channels by setting an optimum threshold level for each channel even when the length of a bus is long. CONSTITUTION:Automatic threshold control circuits 1 - (m) are provided corresponding to the 1st - (m)th channels. Each control circuit has the same constitution of the 1st comparator 11, the 2nd comparator 12, the 1st AND gate 13, the 2nd AND gate 14, and a control circuit 15. The circuits 1 - (m) set optimum threshold levels for the respective channels with gate signals B1 GATE, B2GATE...EmGATE of the respective channels. A control circuit 25 selects an optimum threshold level and data B2 is read out by the 2nd compara tor 24 with the 2nd selected threshold levels T2.1, T2.2...T2.n, passed through an AND gate 24, and outputted as B2DATA from an output terminal 27.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JPS6218847A
source esp@cenet
subjects ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
MULTIPLEX COMMUNICATION
title AUTOMATIC THRESHOLD LEVEL CONTROL SYSTEM
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T15%3A55%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=AMAMIYA%20SHIGEO&rft.date=1987-01-27&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPS6218847A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true