MULTILAYER INTERCONNECTION METHOD OF SEMICONDUCTOR ELEMENT

MULTILAYER INTERCONNECTION METHOD OF SEMICONDUCTOR ELEMENT

PURPOSE:To eliminate defective insulation between wiring layers by eliminating hillock generated at the lower wiring of multilayer interconnection of semiconductor element with reactive ion etching and the hillock of wiring layer with adequate selection of selection ratio between wiring layer and ma...

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1. Verfasser: FURUGUCHI SHIGEO
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator FURUGUCHI SHIGEO
description PURPOSE:To eliminate defective insulation between wiring layers by eliminating hillock generated at the lower wiring of multilayer interconnection of semiconductor element with reactive ion etching and the hillock of wiring layer with adequate selection of selection ratio between wiring layer and mask material. CONSTITUTION:A first insulation layer 1021 is provided at the one main surface of a silicon substrate 101, a first wiring layer 1031 is formed by sputtering, in order to form a wiring pattern. Next, sintering is carried out and hillock 103 is generated on the wiring layer 1031. Next, a mask layer 1 is deposited on the entire part. A polysilicon is selected as a mask material in the thickness of 1mum with a degree of vacuum of 9 pascal, a high frequency RF power of 400W and a flow rate of gas CCl4 of 10cc/min. With this condition, a selection ratio with aluminum becomes 1. Thereby, the part of mask layer 1 becomes thin at the top of hillock and is removed by etching in the early stage. Thereafter, a second insulation layer is deposited.
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CONSTITUTION:A first insulation layer 1021 is provided at the one main surface of a silicon substrate 101, a first wiring layer 1031 is formed by sputtering, in order to form a wiring pattern. Next, sintering is carried out and hillock 103 is generated on the wiring layer 1031. Next, a mask layer 1 is deposited on the entire part. A polysilicon is selected as a mask material in the thickness of 1mum with a degree of vacuum of 9 pascal, a high frequency RF power of 400W and a flow rate of gas CCl4 of 10cc/min. With this condition, a selection ratio with aluminum becomes 1. Thereby, the part of mask layer 1 becomes thin at the top of hillock and is removed by etching in the early stage. Thereafter, a second insulation layer is deposited.</description><edition>4</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1986</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19860425&amp;DB=EPODOC&amp;CC=JP&amp;NR=S6181656A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19860425&amp;DB=EPODOC&amp;CC=JP&amp;NR=S6181656A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FURUGUCHI SHIGEO</creatorcontrib><title>MULTILAYER INTERCONNECTION METHOD OF SEMICONDUCTOR ELEMENT</title><description>PURPOSE:To eliminate defective insulation between wiring layers by eliminating hillock generated at the lower wiring of multilayer interconnection of semiconductor element with reactive ion etching and the hillock of wiring layer with adequate selection of selection ratio between wiring layer and mask material. CONSTITUTION:A first insulation layer 1021 is provided at the one main surface of a silicon substrate 101, a first wiring layer 1031 is formed by sputtering, in order to form a wiring pattern. Next, sintering is carried out and hillock 103 is generated on the wiring layer 1031. Next, a mask layer 1 is deposited on the entire part. A polysilicon is selected as a mask material in the thickness of 1mum with a degree of vacuum of 9 pascal, a high frequency RF power of 400W and a flow rate of gas CCl4 of 10cc/min. With this condition, a selection ratio with aluminum becomes 1. Thereby, the part of mask layer 1 becomes thin at the top of hillock and is removed by etching in the early stage. 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CONSTITUTION:A first insulation layer 1021 is provided at the one main surface of a silicon substrate 101, a first wiring layer 1031 is formed by sputtering, in order to form a wiring pattern. Next, sintering is carried out and hillock 103 is generated on the wiring layer 1031. Next, a mask layer 1 is deposited on the entire part. A polysilicon is selected as a mask material in the thickness of 1mum with a degree of vacuum of 9 pascal, a high frequency RF power of 400W and a flow rate of gas CCl4 of 10cc/min. With this condition, a selection ratio with aluminum becomes 1. Thereby, the part of mask layer 1 becomes thin at the top of hillock and is removed by etching in the early stage. Thereafter, a second insulation layer is deposited.</abstract><edition>4</edition><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title MULTILAYER INTERCONNECTION METHOD OF SEMICONDUCTOR ELEMENT
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