DIGITAL SIGNAL PROCESSING SYSTEM FOR FILTER

PURPOSE:To avoid deterioration of quality and to realize high speed processing without requiring a segmentation processing of a frequency band component by obtaining a real number coefficient matrix in advance and taking an inner product between the matrix and one frame of an input signal so as to output the result. CONSTITUTION:When a frame synchronizing signal is received at an input terminal CK of a binary counter (BCNT), input signals are fetched consecutively and a frame signal just before is outputted according to a read address transmitted from an N-adic counter(CSEL) while buffering. Further, an N-adic counter (RSEL) and a buffer memory (BUFP) output a value corresponding to an element of a real number matrix P according to an address signal being an output of the counter CSEL and a row synchronizing signal. Further, a multiplier (MUL) and an accumulator (ACM) output the sum of N sets of products at two input terminals of the multiplier MUL corresponding to the row synchronizing signal from the counter CSEL.