MEMORY DEVICE FOR SEMICONDUCTOR

PURPOSE:To design stabilization of manufacturing by impressing on a one side main electrode of memory transistors, a gate of no selection line and a substrate successively. CONSTITUTION:Voltage is impressed on memory transistor sources for all bits by the first high voltage impressing means, and vol...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: KIJI AKIO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator KIJI AKIO
description PURPOSE:To design stabilization of manufacturing by impressing on a one side main electrode of memory transistors, a gate of no selection line and a substrate successively. CONSTITUTION:Voltage is impressed on memory transistor sources for all bits by the first high voltage impressing means, and voltage is applied only on a gate for a memory transistor of no selection line by the second high voltage applying step. Thereafter, voltage is impressed on a memory substrate by the third high voltage impressing means. In regard to memory transistors M11, M12, the threshold VTH moves in the depressional direction by potential difference between the gate and the substrate to eliminate contents of memory. On the other hand, the threshold is not changed, in regard to no selection memory transistors M21, M22, because of no potential difference between the gate and the substrate, and contents of the memory are not eliminated. Thereafter, the memory substrate must be back to Vss, gate to Vss, and finally the source to Vss. Thus, impressing high voltage successively, stabilized production of non-volatile memory becomes possible.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPS6124098A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPS6124098A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPS6124098A3</originalsourceid><addsrcrecordid>eNrjZJD3dfX1D4pUcHEN83R2VXDzD1IIdvX1dPb3cwl1DvEP4mFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8V4BwWaGRiYGlhaOxkQoAQClDyGn</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MEMORY DEVICE FOR SEMICONDUCTOR</title><source>esp@cenet</source><creator>KIJI AKIO</creator><creatorcontrib>KIJI AKIO</creatorcontrib><description>PURPOSE:To design stabilization of manufacturing by impressing on a one side main electrode of memory transistors, a gate of no selection line and a substrate successively. CONSTITUTION:Voltage is impressed on memory transistor sources for all bits by the first high voltage impressing means, and voltage is applied only on a gate for a memory transistor of no selection line by the second high voltage applying step. Thereafter, voltage is impressed on a memory substrate by the third high voltage impressing means. In regard to memory transistors M11, M12, the threshold VTH moves in the depressional direction by potential difference between the gate and the substrate to eliminate contents of memory. On the other hand, the threshold is not changed, in regard to no selection memory transistors M21, M22, because of no potential difference between the gate and the substrate, and contents of the memory are not eliminated. Thereafter, the memory substrate must be back to Vss, gate to Vss, and finally the source to Vss. Thus, impressing high voltage successively, stabilized production of non-volatile memory becomes possible.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>1986</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19860201&amp;DB=EPODOC&amp;CC=JP&amp;NR=S6124098A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19860201&amp;DB=EPODOC&amp;CC=JP&amp;NR=S6124098A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KIJI AKIO</creatorcontrib><title>MEMORY DEVICE FOR SEMICONDUCTOR</title><description>PURPOSE:To design stabilization of manufacturing by impressing on a one side main electrode of memory transistors, a gate of no selection line and a substrate successively. CONSTITUTION:Voltage is impressed on memory transistor sources for all bits by the first high voltage impressing means, and voltage is applied only on a gate for a memory transistor of no selection line by the second high voltage applying step. Thereafter, voltage is impressed on a memory substrate by the third high voltage impressing means. In regard to memory transistors M11, M12, the threshold VTH moves in the depressional direction by potential difference between the gate and the substrate to eliminate contents of memory. On the other hand, the threshold is not changed, in regard to no selection memory transistors M21, M22, because of no potential difference between the gate and the substrate, and contents of the memory are not eliminated. Thereafter, the memory substrate must be back to Vss, gate to Vss, and finally the source to Vss. Thus, impressing high voltage successively, stabilized production of non-volatile memory becomes possible.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1986</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJD3dfX1D4pUcHEN83R2VXDzD1IIdvX1dPb3cwl1DvEP4mFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8V4BwWaGRiYGlhaOxkQoAQClDyGn</recordid><startdate>19860201</startdate><enddate>19860201</enddate><creator>KIJI AKIO</creator><scope>EVB</scope></search><sort><creationdate>19860201</creationdate><title>MEMORY DEVICE FOR SEMICONDUCTOR</title><author>KIJI AKIO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS6124098A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1986</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>KIJI AKIO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KIJI AKIO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MEMORY DEVICE FOR SEMICONDUCTOR</title><date>1986-02-01</date><risdate>1986</risdate><abstract>PURPOSE:To design stabilization of manufacturing by impressing on a one side main electrode of memory transistors, a gate of no selection line and a substrate successively. CONSTITUTION:Voltage is impressed on memory transistor sources for all bits by the first high voltage impressing means, and voltage is applied only on a gate for a memory transistor of no selection line by the second high voltage applying step. Thereafter, voltage is impressed on a memory substrate by the third high voltage impressing means. In regard to memory transistors M11, M12, the threshold VTH moves in the depressional direction by potential difference between the gate and the substrate to eliminate contents of memory. On the other hand, the threshold is not changed, in regard to no selection memory transistors M21, M22, because of no potential difference between the gate and the substrate, and contents of the memory are not eliminated. Thereafter, the memory substrate must be back to Vss, gate to Vss, and finally the source to Vss. Thus, impressing high voltage successively, stabilized production of non-volatile memory becomes possible.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JPS6124098A
source esp@cenet
subjects INFORMATION STORAGE
PHYSICS
STATIC STORES
title MEMORY DEVICE FOR SEMICONDUCTOR
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-19T18%3A39%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KIJI%20AKIO&rft.date=1986-02-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPS6124098A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true