DIGITAL SIGNAL REPRODUCING SYSTEM
PURPOSE:To shorten the lead-in time and to shorten the stabilizing time of a clock frequency for reproducing a digital signal by providing a frequency counter and an arithmetic circuit for differentiating its output and executing a frequency lead-in. CONSTITUTION:In case of reproducing a digital sig...
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| creator | YABE MASAYUKI |
| description | PURPOSE:To shorten the lead-in time and to shorten the stabilizing time of a clock frequency for reproducing a digital signal by providing a frequency counter and an arithmetic circuit for differentiating its output and executing a frequency lead-in. CONSTITUTION:In case of reproducing a digital signal, first of all, the output frequency f0 of a crystal oscillator 5 is measured by a frequency counter 8 by using a digital signal fi as a sampling frequency. Subsequently, this output is differentiated by an operating circuit 9, the inclination of a frequency rise characteristic of the oscillator 5 is obtained, quantized and outputted to a digital phase locked loop circuit DPLL 4 as a control signal for controlling the phase step width of the DPLL 4. In the DPLL 4, in accordance with the output of the circuit 9, the larger its value is, the larger the phase step width is set and a frequency lead-in is executed so that the output frequency fd of the DPLL 4 coincides with the transmission rate of the signal fi. In this way, the lead-in time can be shortened and the stabilizing time of a clock frequency for reproducing a digital signal, etc. can be shortened. |
| format | Patent |
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CONSTITUTION:In case of reproducing a digital signal, first of all, the output frequency f0 of a crystal oscillator 5 is measured by a frequency counter 8 by using a digital signal fi as a sampling frequency. Subsequently, this output is differentiated by an operating circuit 9, the inclination of a frequency rise characteristic of the oscillator 5 is obtained, quantized and outputted to a digital phase locked loop circuit DPLL 4 as a control signal for controlling the phase step width of the DPLL 4. In the DPLL 4, in accordance with the output of the circuit 9, the larger its value is, the larger the phase step width is set and a frequency lead-in is executed so that the output frequency fd of the DPLL 4 coincides with the transmission rate of the signal fi. In this way, the lead-in time can be shortened and the stabilizing time of a clock frequency for reproducing a digital signal, etc. can be shortened.</description><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>1986</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19861027&DB=EPODOC&CC=JP&NR=S61240733A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19861027&DB=EPODOC&CC=JP&NR=S61240733A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YABE MASAYUKI</creatorcontrib><title>DIGITAL SIGNAL REPRODUCING SYSTEM</title><description>PURPOSE:To shorten the lead-in time and to shorten the stabilizing time of a clock frequency for reproducing a digital signal by providing a frequency counter and an arithmetic circuit for differentiating its output and executing a frequency lead-in. CONSTITUTION:In case of reproducing a digital signal, first of all, the output frequency f0 of a crystal oscillator 5 is measured by a frequency counter 8 by using a digital signal fi as a sampling frequency. Subsequently, this output is differentiated by an operating circuit 9, the inclination of a frequency rise characteristic of the oscillator 5 is obtained, quantized and outputted to a digital phase locked loop circuit DPLL 4 as a control signal for controlling the phase step width of the DPLL 4. In the DPLL 4, in accordance with the output of the circuit 9, the larger its value is, the larger the phase step width is set and a frequency lead-in is executed so that the output frequency fd of the DPLL 4 coincides with the transmission rate of the signal fi. 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CONSTITUTION:In case of reproducing a digital signal, first of all, the output frequency f0 of a crystal oscillator 5 is measured by a frequency counter 8 by using a digital signal fi as a sampling frequency. Subsequently, this output is differentiated by an operating circuit 9, the inclination of a frequency rise characteristic of the oscillator 5 is obtained, quantized and outputted to a digital phase locked loop circuit DPLL 4 as a control signal for controlling the phase step width of the DPLL 4. In the DPLL 4, in accordance with the output of the circuit 9, the larger its value is, the larger the phase step width is set and a frequency lead-in is executed so that the output frequency fd of the DPLL 4 coincides with the transmission rate of the signal fi. In this way, the lead-in time can be shortened and the stabilizing time of a clock frequency for reproducing a digital signal, etc. can be shortened.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
| title | DIGITAL SIGNAL REPRODUCING SYSTEM |
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