LSI ASSEMBLAGE
PURPOSE:To obtain LSI assemblages capable of simple LSI connection and excellent in reliability by a method wherein LSIs are arranged at the center and in the periphery, between which buses are arranged. CONSTITUTION:The first LSI group at the center and the second LSI group in the periphery are arr...
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creator | HAMADA NAGAHARU NAKAJIMA KEISUKE |
description | PURPOSE:To obtain LSI assemblages capable of simple LSI connection and excellent in reliability by a method wherein LSIs are arranged at the center and in the periphery, between which buses are arranged. CONSTITUTION:The first LSI group at the center and the second LSI group in the periphery are arranged at a required interval, between which buses 201, 202, 203...n-1, n, 501 and 502 are made to run in ring form. The LSI group at the center is provided with processors having relatively a large number of connections to the buses. The periphery of a chip is provided with memories and peripheral controllers. Wirings 601, 602, and the like selectively connect the busses 201, 202, 203...n-1, n, 501, 502 to each LSI. Then the wiring between bus components becomes extremely simple, and the manufacturing cost for LSI connection can be markedly reduced. Besides, the bus reliability can be highly enhanced by making buses in ring form. |
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CONSTITUTION:The first LSI group at the center and the second LSI group in the periphery are arranged at a required interval, between which buses 201, 202, 203...n-1, n, 501 and 502 are made to run in ring form. The LSI group at the center is provided with processors having relatively a large number of connections to the buses. The periphery of a chip is provided with memories and peripheral controllers. Wirings 601, 602, and the like selectively connect the busses 201, 202, 203...n-1, n, 501, 502 to each LSI. Then the wiring between bus components becomes extremely simple, and the manufacturing cost for LSI connection can be markedly reduced. Besides, the bus reliability can be highly enhanced by making buses in ring form.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1986</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19860129&DB=EPODOC&CC=JP&NR=S6120349A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19860129&DB=EPODOC&CC=JP&NR=S6120349A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HAMADA NAGAHARU</creatorcontrib><creatorcontrib>NAKAJIMA KEISUKE</creatorcontrib><title>LSI ASSEMBLAGE</title><description>PURPOSE:To obtain LSI assemblages capable of simple LSI connection and excellent in reliability by a method wherein LSIs are arranged at the center and in the periphery, between which buses are arranged. CONSTITUTION:The first LSI group at the center and the second LSI group in the periphery are arranged at a required interval, between which buses 201, 202, 203...n-1, n, 501 and 502 are made to run in ring form. The LSI group at the center is provided with processors having relatively a large number of connections to the buses. The periphery of a chip is provided with memories and peripheral controllers. Wirings 601, 602, and the like selectively connect the busses 201, 202, 203...n-1, n, 501, 502 to each LSI. Then the wiring between bus components becomes extremely simple, and the manufacturing cost for LSI connection can be markedly reduced. Besides, the bus reliability can be highly enhanced by making buses in ring form.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1986</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZODzCfZUcAwOdvV18nF0d-VhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfFeAcFmhkYGxiaWjsZEKAEAj6QcuQ</recordid><startdate>19860129</startdate><enddate>19860129</enddate><creator>HAMADA NAGAHARU</creator><creator>NAKAJIMA KEISUKE</creator><scope>EVB</scope></search><sort><creationdate>19860129</creationdate><title>LSI ASSEMBLAGE</title><author>HAMADA NAGAHARU ; NAKAJIMA KEISUKE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS6120349A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1986</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HAMADA NAGAHARU</creatorcontrib><creatorcontrib>NAKAJIMA KEISUKE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HAMADA NAGAHARU</au><au>NAKAJIMA KEISUKE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>LSI ASSEMBLAGE</title><date>1986-01-29</date><risdate>1986</risdate><abstract>PURPOSE:To obtain LSI assemblages capable of simple LSI connection and excellent in reliability by a method wherein LSIs are arranged at the center and in the periphery, between which buses are arranged. CONSTITUTION:The first LSI group at the center and the second LSI group in the periphery are arranged at a required interval, between which buses 201, 202, 203...n-1, n, 501 and 502 are made to run in ring form. The LSI group at the center is provided with processors having relatively a large number of connections to the buses. The periphery of a chip is provided with memories and peripheral controllers. Wirings 601, 602, and the like selectively connect the busses 201, 202, 203...n-1, n, 501, 502 to each LSI. Then the wiring between bus components becomes extremely simple, and the manufacturing cost for LSI connection can be markedly reduced. Besides, the bus reliability can be highly enhanced by making buses in ring form.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | LSI ASSEMBLAGE |
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