GATE ARRAY

PURPOSE:To reduce the capacity between wiring layers and to reduce the adverse effects to the operational speed of a gate array, by arranging wires passing over a memory region such that they are bent in a stepped manner so as to reduce wiring parallel with the memory circuit. CONSTITUTION:Zigzag si...

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Hauptverfasser:	OGATA HARUMI, NISHIKAWA YASUHIRO, KAWACHI KAZUYUKI
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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creator	OGATA HARUMI NISHIKAWA YASUHIRO KAWACHI KAZUYUKI
description	PURPOSE:To reduce the capacity between wiring layers and to reduce the adverse effects to the operational speed of a gate array, by arranging wires passing over a memory region such that they are bent in a stepped manner so as to reduce wiring parallel with the memory circuit. CONSTITUTION:Zigzag signal lines SL0 are provided such that they are bent once into an L-shape in the region of RAM. In this case, the maximum capacity of one data line DL in the lower layer and of one signal line SL of the upper layer is reduced to one half. When the signal lines SL0 in the upper layer are bent twice, the maximum wiring capacity between the signal lines can be reduced to about one third. Accordingly, the high-density gate array is allowed to operate more rapidly.
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CONSTITUTION:Zigzag signal lines SL0 are provided such that they are bent once into an L-shape in the region of RAM. In this case, the maximum capacity of one data line DL in the lower layer and of one signal line SL of the upper layer is reduced to one half. When the signal lines SL0 in the upper layer are bent twice, the maximum wiring capacity between the signal lines can be reduced to about one third. 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CONSTITUTION:Zigzag signal lines SL0 are provided such that they are bent once into an L-shape in the region of RAM. In this case, the maximum capacity of one data line DL in the lower layer and of one signal line SL of the upper layer is reduced to one half. When the signal lines SL0 in the upper layer are bent twice, the maximum wiring capacity between the signal lines can be reduced to about one third. Accordingly, the high-density gate array is allowed to operate more rapidly.</abstract><oa>free_for_read</oa></addata></record>
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subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	GATE ARRAY
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