JPS6023379B
PURPOSE:To indicate retrying operation by detecting the presence of an error while sending read information from a memory unit to a processor regardless of whether the information has an error or not, and then by interrupting the process of the processor when the error is detected. CONSTITUTION:Info...
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| creator | MATSURA TSUGUO OOBA TAKAO KIRYU YOSHIO |
| description | PURPOSE:To indicate retrying operation by detecting the presence of an error while sending read information from a memory unit to a processor regardless of whether the information has an error or not, and then by interrupting the process of the processor when the error is detected. CONSTITUTION:Information 3 read out from memory part 11 by access request 1 from CPU is inputted to check circuit 12 and error correction circuit 13. Since error correction circuit 13 is normally OFF, it is sent as read information 5 of MS to CPU and processed there. In parallel to this, check circuit 12 checks read information 3 and if an error is detected, error signal 6 is sent to retrying control circuit 14 of CPU, thereby indicating the retrying operation of the pre-processing of CPU. Then, CPU indicates the transmission of retrying signal 2 to retrying control circuit 14 to put error correction circuit 13 into operation, and retrying command signal 7 actuates access generating circuit 15 to send request 1 from CPU to MS. |
| format | Patent |
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CONSTITUTION:Information 3 read out from memory part 11 by access request 1 from CPU is inputted to check circuit 12 and error correction circuit 13. Since error correction circuit 13 is normally OFF, it is sent as read information 5 of MS to CPU and processed there. In parallel to this, check circuit 12 checks read information 3 and if an error is detected, error signal 6 is sent to retrying control circuit 14 of CPU, thereby indicating the retrying operation of the pre-processing of CPU. Then, CPU indicates the transmission of retrying signal 2 to retrying control circuit 14 to put error correction circuit 13 into operation, and retrying command signal 7 actuates access generating circuit 15 to send request 1 from CPU to MS.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>1985</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19850607&DB=EPODOC&CC=JP&NR=S6023379B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19850607&DB=EPODOC&CC=JP&NR=S6023379B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MATSURA TSUGUO</creatorcontrib><creatorcontrib>OOBA TAKAO</creatorcontrib><creatorcontrib>KIRYU YOSHIO</creatorcontrib><title>JPS6023379B</title><description>PURPOSE:To indicate retrying operation by detecting the presence of an error while sending read information from a memory unit to a processor regardless of whether the information has an error or not, and then by interrupting the process of the processor when the error is detected. CONSTITUTION:Information 3 read out from memory part 11 by access request 1 from CPU is inputted to check circuit 12 and error correction circuit 13. Since error correction circuit 13 is normally OFF, it is sent as read information 5 of MS to CPU and processed there. In parallel to this, check circuit 12 checks read information 3 and if an error is detected, error signal 6 is sent to retrying control circuit 14 of CPU, thereby indicating the retrying operation of the pre-processing of CPU. Then, CPU indicates the transmission of retrying signal 2 to retrying control circuit 14 to put error correction circuit 13 into operation, and retrying command signal 7 actuates access generating circuit 15 to send request 1 from CPU to MS.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1985</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOD2Cgg2MzAyNja3dOJhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFIOpyMjIlSBACENBxv</recordid><startdate>19850607</startdate><enddate>19850607</enddate><creator>MATSURA TSUGUO</creator><creator>OOBA TAKAO</creator><creator>KIRYU YOSHIO</creator><scope>EVB</scope></search><sort><creationdate>19850607</creationdate><title>JPS6023379B</title><author>MATSURA TSUGUO ; OOBA TAKAO ; KIRYU YOSHIO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS6023379BB23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1985</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>MATSURA TSUGUO</creatorcontrib><creatorcontrib>OOBA TAKAO</creatorcontrib><creatorcontrib>KIRYU YOSHIO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MATSURA TSUGUO</au><au>OOBA TAKAO</au><au>KIRYU YOSHIO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>JPS6023379B</title><date>1985-06-07</date><risdate>1985</risdate><abstract>PURPOSE:To indicate retrying operation by detecting the presence of an error while sending read information from a memory unit to a processor regardless of whether the information has an error or not, and then by interrupting the process of the processor when the error is detected. CONSTITUTION:Information 3 read out from memory part 11 by access request 1 from CPU is inputted to check circuit 12 and error correction circuit 13. Since error correction circuit 13 is normally OFF, it is sent as read information 5 of MS to CPU and processed there. In parallel to this, check circuit 12 checks read information 3 and if an error is detected, error signal 6 is sent to retrying control circuit 14 of CPU, thereby indicating the retrying operation of the pre-processing of CPU. Then, CPU indicates the transmission of retrying signal 2 to retrying control circuit 14 to put error correction circuit 13 into operation, and retrying command signal 7 actuates access generating circuit 15 to send request 1 from CPU to MS.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
| title | JPS6023379B |
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