INPUT/OUTPUT CONTROL DEVICE PROVIDED WITH MEMORY PROTECTING FUNCTION
PURPOSE:To eliminate ineffective hardware in a main memory control device and heighten efficiency of use of hardware by arranging and dispersing the holding mechanism of memory protection information and memory protection judging function in an individual input/output control device instead of arran...
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| creator | HIRAMATSU JIYUNICHI |
| description | PURPOSE:To eliminate ineffective hardware in a main memory control device and heighten efficiency of use of hardware by arranging and dispersing the holding mechanism of memory protection information and memory protection judging function in an individual input/output control device instead of arranging them in a main memory control device. CONSTITUTION:After the completion of storing the first address and the last address in a main memory 6 accessible to a memory protection information storing register 20, a CPU3 gives the command of direct memory access from an input/output device 12a to a main memory 6. On receiving the command, a main control device 21 reads data from the input/output device 12a and supplies main memory address to a memory protection judging circuit 24. When the main memory address is in the middle of the first address and last address of the register 20, the memory protection judging circuit 24 judge that access is possible, and output a bus access permission signal on a signal line. When it is not in the middle, a bus access inhibition signal is outputted. |
| format | Patent |
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CONSTITUTION:After the completion of storing the first address and the last address in a main memory 6 accessible to a memory protection information storing register 20, a CPU3 gives the command of direct memory access from an input/output device 12a to a main memory 6. On receiving the command, a main control device 21 reads data from the input/output device 12a and supplies main memory address to a memory protection judging circuit 24. When the main memory address is in the middle of the first address and last address of the register 20, the memory protection judging circuit 24 judge that access is possible, and output a bus access permission signal on a signal line. When it is not in the middle, a bus access inhibition signal is outputted.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1984</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19841129&DB=EPODOC&CC=JP&NR=S59210598A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19841129&DB=EPODOC&CC=JP&NR=S59210598A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HIRAMATSU JIYUNICHI</creatorcontrib><title>INPUT/OUTPUT CONTROL DEVICE PROVIDED WITH MEMORY PROTECTING FUNCTION</title><description>PURPOSE:To eliminate ineffective hardware in a main memory control device and heighten efficiency of use of hardware by arranging and dispersing the holding mechanism of memory protection information and memory protection judging function in an individual input/output control device instead of arranging them in a main memory control device. CONSTITUTION:After the completion of storing the first address and the last address in a main memory 6 accessible to a memory protection information storing register 20, a CPU3 gives the command of direct memory access from an input/output device 12a to a main memory 6. On receiving the command, a main control device 21 reads data from the input/output device 12a and supplies main memory address to a memory protection judging circuit 24. When the main memory address is in the middle of the first address and last address of the register 20, the memory protection judging circuit 24 judge that access is possible, and output a bus access permission signal on a signal line. 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CONSTITUTION:After the completion of storing the first address and the last address in a main memory 6 accessible to a memory protection information storing register 20, a CPU3 gives the command of direct memory access from an input/output device 12a to a main memory 6. On receiving the command, a main control device 21 reads data from the input/output device 12a and supplies main memory address to a memory protection judging circuit 24. When the main memory address is in the middle of the first address and last address of the register 20, the memory protection judging circuit 24 judge that access is possible, and output a bus access permission signal on a signal line. When it is not in the middle, a bus access inhibition signal is outputted.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | INPUT/OUTPUT CONTROL DEVICE PROVIDED WITH MEMORY PROTECTING FUNCTION |
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