REFRESH CONTROL SYSTEM OF MEMORY DEVICE

REFRESH CONTROL SYSTEM OF MEMORY DEVICE

PURPOSE:To improve the performance, by indicating refresh of the same block in a refresh cycle times for plural number of times so as to reduce the probability of processing wait of memory access request generated through the comfliction between the memory access request and the refresh request. CON...

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1. Verfasser: ONIZUKA NOBUHIKO
Format: Patent
Sprache:eng
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INFORMATION STORAGE
PHYSICS
STATIC STORES
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creator ONIZUKA NOBUHIKO
description PURPOSE:To improve the performance, by indicating refresh of the same block in a refresh cycle times for plural number of times so as to reduce the probability of processing wait of memory access request generated through the comfliction between the memory access request and the refresh request. CONSTITUTION:In Figure, 1 is a memory access device, 2 is a memory device, and 3 is a refresh control circuit, and 4 is a refresh counter (RFC1-n) to count the number of time of the refresh request not processed due to the confliction with the memory access request REQ among refresh requests REFREQ1-(n) generated at each refresh block of an IC-RAM. The limit of the processing waiting of the refresh request is detected with the value of the refresh counter, and only when the limit is detected, the refresh request is processed with priority over the memory access request and in other cases, the memory access request is processed over the refresh request. Then, the number of times of waiting of processing of the memory access request generated from the confliction with the refresh request is decreased.
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CONSTITUTION:In Figure, 1 is a memory access device, 2 is a memory device, and 3 is a refresh control circuit, and 4 is a refresh counter (RFC1-n) to count the number of time of the refresh request not processed due to the confliction with the memory access request REQ among refresh requests REFREQ1-(n) generated at each refresh block of an IC-RAM. The limit of the processing waiting of the refresh request is detected with the value of the refresh counter, and only when the limit is detected, the refresh request is processed with priority over the memory access request and in other cases, the memory access request is processed over the refresh request. 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CONSTITUTION:In Figure, 1 is a memory access device, 2 is a memory device, and 3 is a refresh control circuit, and 4 is a refresh counter (RFC1-n) to count the number of time of the refresh request not processed due to the confliction with the memory access request REQ among refresh requests REFREQ1-(n) generated at each refresh block of an IC-RAM. The limit of the processing waiting of the refresh request is detected with the value of the refresh counter, and only when the limit is detected, the refresh request is processed with priority over the memory access request and in other cases, the memory access request is processed over the refresh request. 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CONSTITUTION:In Figure, 1 is a memory access device, 2 is a memory device, and 3 is a refresh control circuit, and 4 is a refresh counter (RFC1-n) to count the number of time of the refresh request not processed due to the confliction with the memory access request REQ among refresh requests REFREQ1-(n) generated at each refresh block of an IC-RAM. The limit of the processing waiting of the refresh request is detected with the value of the refresh counter, and only when the limit is detected, the refresh request is processed with priority over the memory access request and in other cases, the memory access request is processed over the refresh request. Then, the number of times of waiting of processing of the memory access request generated from the confliction with the refresh request is decreased.</abstract><oa>free_for_read</oa></addata></record>
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subjects INFORMATION STORAGE
PHYSICS
STATIC STORES
title REFRESH CONTROL SYSTEM OF MEMORY DEVICE
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