ROM CHECKING SYSTEM

PURPOSE:To execute completely an ROM check through a few external output terminal by outputting serially the output of a latched ROM in accordance with a switching signal, and checking by one bit each of contents of the ROM. CONSTITUTION:A data of (n)-bit, etc. from the ROM6 is impressed and latched...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: SAITOU KATSUMI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator SAITOU KATSUMI
description PURPOSE:To execute completely an ROM check through a few external output terminal by outputting serially the output of a latched ROM in accordance with a switching signal, and checking by one bit each of contents of the ROM. CONSTITUTION:A data of (n)-bit, etc. from the ROM6 is impressed and latched to an input terminal R of (n) flip-flops FF1-FFn for forming a latching circuit 7. The output of the flip-flop of a lower stage except the flip-flop FF1 is impressed to the input terminal I of these flip-flops. Subsequently, the flip-flop is brought to a multistage operation in accordance with a switching signal Te to output a latch output serially and successively from the flip-flops FF1, FF2-, and compared with an instruction data stored in an RAM, etc. through a common external output terminal to check the ROM. According to this constitution, the ROM check can be executed completely through a few external output terminal.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPS59171097A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPS59171097A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPS59171097A3</originalsourceid><addsrcrecordid>eNrjZBAO8vdVcPZwdfb29HNXCI4MDnH15WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8V4BwaaWhuaGBpbmjsbEqAEAYgwerw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ROM CHECKING SYSTEM</title><source>esp@cenet</source><creator>SAITOU KATSUMI</creator><creatorcontrib>SAITOU KATSUMI</creatorcontrib><description>PURPOSE:To execute completely an ROM check through a few external output terminal by outputting serially the output of a latched ROM in accordance with a switching signal, and checking by one bit each of contents of the ROM. CONSTITUTION:A data of (n)-bit, etc. from the ROM6 is impressed and latched to an input terminal R of (n) flip-flops FF1-FFn for forming a latching circuit 7. The output of the flip-flop of a lower stage except the flip-flop FF1 is impressed to the input terminal I of these flip-flops. Subsequently, the flip-flop is brought to a multistage operation in accordance with a switching signal Te to output a latch output serially and successively from the flip-flops FF1, FF2-, and compared with an instruction data stored in an RAM, etc. through a common external output terminal to check the ROM. According to this constitution, the ROM check can be executed completely through a few external output terminal.</description><language>eng</language><subject>INFORMATION STORAGE ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; STATIC STORES ; TESTING</subject><creationdate>1984</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19840927&amp;DB=EPODOC&amp;CC=JP&amp;NR=S59171097A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19840927&amp;DB=EPODOC&amp;CC=JP&amp;NR=S59171097A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SAITOU KATSUMI</creatorcontrib><title>ROM CHECKING SYSTEM</title><description>PURPOSE:To execute completely an ROM check through a few external output terminal by outputting serially the output of a latched ROM in accordance with a switching signal, and checking by one bit each of contents of the ROM. CONSTITUTION:A data of (n)-bit, etc. from the ROM6 is impressed and latched to an input terminal R of (n) flip-flops FF1-FFn for forming a latching circuit 7. The output of the flip-flop of a lower stage except the flip-flop FF1 is impressed to the input terminal I of these flip-flops. Subsequently, the flip-flop is brought to a multistage operation in accordance with a switching signal Te to output a latch output serially and successively from the flip-flops FF1, FF2-, and compared with an instruction data stored in an RAM, etc. through a common external output terminal to check the ROM. According to this constitution, the ROM check can be executed completely through a few external output terminal.</description><subject>INFORMATION STORAGE</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1984</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAO8vdVcPZwdfb29HNXCI4MDnH15WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8V4BwaaWhuaGBpbmjsbEqAEAYgwerw</recordid><startdate>19840927</startdate><enddate>19840927</enddate><creator>SAITOU KATSUMI</creator><scope>EVB</scope></search><sort><creationdate>19840927</creationdate><title>ROM CHECKING SYSTEM</title><author>SAITOU KATSUMI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS59171097A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1984</creationdate><topic>INFORMATION STORAGE</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>SAITOU KATSUMI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SAITOU KATSUMI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ROM CHECKING SYSTEM</title><date>1984-09-27</date><risdate>1984</risdate><abstract>PURPOSE:To execute completely an ROM check through a few external output terminal by outputting serially the output of a latched ROM in accordance with a switching signal, and checking by one bit each of contents of the ROM. CONSTITUTION:A data of (n)-bit, etc. from the ROM6 is impressed and latched to an input terminal R of (n) flip-flops FF1-FFn for forming a latching circuit 7. The output of the flip-flop of a lower stage except the flip-flop FF1 is impressed to the input terminal I of these flip-flops. Subsequently, the flip-flop is brought to a multistage operation in accordance with a switching signal Te to output a latch output serially and successively from the flip-flops FF1, FF2-, and compared with an instruction data stored in an RAM, etc. through a common external output terminal to check the ROM. According to this constitution, the ROM check can be executed completely through a few external output terminal.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JPS59171097A
source esp@cenet
subjects INFORMATION STORAGE
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
STATIC STORES
TESTING
title ROM CHECKING SYSTEM
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-07T18%3A54%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SAITOU%20KATSUMI&rft.date=1984-09-27&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPS59171097A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true