CONTROL SYSTEM OF STORAGE DEVICE
PURPOSE:To use memories with different storage capacity efficiently by allowing an access control part to select a memory unit while referring different storage capacity included in plural memory units to convert an address signal. CONSTITUTION:The memory units 10aa-10nn having different storage cap...
Gespeichert in:
1. Verfasser: | |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | FUJISAKI KAZUO |
description | PURPOSE:To use memories with different storage capacity efficiently by allowing an access control part to select a memory unit while referring different storage capacity included in plural memory units to convert an address signal. CONSTITUTION:The memory units 10aa-10nn having different storage capacity use a data bus and an address bus in common and are controlled by a memory access control part (MAC) 30a. Each memory unit 10ii has a memory unit mounting storage capacity specifying circuit 15 in addition to a memory array 11, an address register 12, a write data register 13, and a read data register 14 and transfers and holds the data to/in a memory constitution control circuit 31. The MAC 30 selects each memory unit 10ii and accesses an address register 12 while referring the mounted storage capacity of each memory unit 10ii to convert an input address signal. Thus, the memory units having different storage capacity can be efficiently used. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPS59148963A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPS59148963A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPS59148963A3</originalsourceid><addsrcrecordid>eNrjZFBw9vcLCfL3UQiODA5x9VXwd1MIDvEPcnR3VXBxDfN0duVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAcGmloYmFpZmxo7GxKgBAAY_Ilk</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CONTROL SYSTEM OF STORAGE DEVICE</title><source>esp@cenet</source><creator>FUJISAKI KAZUO</creator><creatorcontrib>FUJISAKI KAZUO</creatorcontrib><description>PURPOSE:To use memories with different storage capacity efficiently by allowing an access control part to select a memory unit while referring different storage capacity included in plural memory units to convert an address signal. CONSTITUTION:The memory units 10aa-10nn having different storage capacity use a data bus and an address bus in common and are controlled by a memory access control part (MAC) 30a. Each memory unit 10ii has a memory unit mounting storage capacity specifying circuit 15 in addition to a memory array 11, an address register 12, a write data register 13, and a read data register 14 and transfers and holds the data to/in a memory constitution control circuit 31. The MAC 30 selects each memory unit 10ii and accesses an address register 12 while referring the mounted storage capacity of each memory unit 10ii to convert an input address signal. Thus, the memory units having different storage capacity can be efficiently used.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1984</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19840825&DB=EPODOC&CC=JP&NR=S59148963A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19840825&DB=EPODOC&CC=JP&NR=S59148963A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FUJISAKI KAZUO</creatorcontrib><title>CONTROL SYSTEM OF STORAGE DEVICE</title><description>PURPOSE:To use memories with different storage capacity efficiently by allowing an access control part to select a memory unit while referring different storage capacity included in plural memory units to convert an address signal. CONSTITUTION:The memory units 10aa-10nn having different storage capacity use a data bus and an address bus in common and are controlled by a memory access control part (MAC) 30a. Each memory unit 10ii has a memory unit mounting storage capacity specifying circuit 15 in addition to a memory array 11, an address register 12, a write data register 13, and a read data register 14 and transfers and holds the data to/in a memory constitution control circuit 31. The MAC 30 selects each memory unit 10ii and accesses an address register 12 while referring the mounted storage capacity of each memory unit 10ii to convert an input address signal. Thus, the memory units having different storage capacity can be efficiently used.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1984</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFBw9vcLCfL3UQiODA5x9VXwd1MIDvEPcnR3VXBxDfN0duVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAcGmloYmFpZmxo7GxKgBAAY_Ilk</recordid><startdate>19840825</startdate><enddate>19840825</enddate><creator>FUJISAKI KAZUO</creator><scope>EVB</scope></search><sort><creationdate>19840825</creationdate><title>CONTROL SYSTEM OF STORAGE DEVICE</title><author>FUJISAKI KAZUO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS59148963A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1984</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>FUJISAKI KAZUO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FUJISAKI KAZUO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CONTROL SYSTEM OF STORAGE DEVICE</title><date>1984-08-25</date><risdate>1984</risdate><abstract>PURPOSE:To use memories with different storage capacity efficiently by allowing an access control part to select a memory unit while referring different storage capacity included in plural memory units to convert an address signal. CONSTITUTION:The memory units 10aa-10nn having different storage capacity use a data bus and an address bus in common and are controlled by a memory access control part (MAC) 30a. Each memory unit 10ii has a memory unit mounting storage capacity specifying circuit 15 in addition to a memory array 11, an address register 12, a write data register 13, and a read data register 14 and transfers and holds the data to/in a memory constitution control circuit 31. The MAC 30 selects each memory unit 10ii and accesses an address register 12 while referring the mounted storage capacity of each memory unit 10ii to convert an input address signal. Thus, the memory units having different storage capacity can be efficiently used.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_JPS59148963A |
source | esp@cenet |
subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | CONTROL SYSTEM OF STORAGE DEVICE |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-04T10%3A16%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=FUJISAKI%20KAZUO&rft.date=1984-08-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPS59148963A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |