FLOATING GATE TYPE NONVOLATILE MOS SEMICONDUCTOR MEMORY DEVICE
PURPOSE:To make writing characteristics excellent and to prevent soft writing, by separately arranging a write only transistor, which commonly posseses a floating gate and is easy to write, and a read only transistor, which is hard to write, on one memory cell. CONSTITUTION:A source part 20 is commo...
Gespeichert in:
Hauptverfasser: | , , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | MIYOSHI HIROKAZU NISHIMOTO AKIRA TAKAHASHI HIRONARI NAKAJIMA MORIYOSHI ANDOU AKIRA MATSUNO YOUKO |
description | PURPOSE:To make writing characteristics excellent and to prevent soft writing, by separately arranging a write only transistor, which commonly posseses a floating gate and is easy to write, and a read only transistor, which is hard to write, on one memory cell. CONSTITUTION:A source part 20 is commonly used for both writing and reading. A drain part is divided into a write only part 21 and a read only part 22 by a field oxide silicon film 13. The interval between the source part 20 on the write only side and the drain part 21 is made to be, e.g., as short as about 3.5mum, and electrons are injected. Since a floating gate is in common, the electrons are distributed on the read only side. Meanwhile, the interval between the source part 20 on the read only side is made to be, e.g., as long as about 5mum, and electric field strength between both parts 20 and 22 is made weak. Thus, soft writing can be reduced to the minimum. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPS59117270A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPS59117270A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPS59117270A3</originalsourceid><addsrcrecordid>eNrjZLBz8_F3DPH0c1dwdwxxVQiJDHBV8PP3C_P3AYr6uCr4-gcrBLv6ejr7-7mEOof4Byn4uvr6B0UquLiGeTq78jCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSSeK-AYFNLQ0NzI3MDR2Ni1AAAgN8qtg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>FLOATING GATE TYPE NONVOLATILE MOS SEMICONDUCTOR MEMORY DEVICE</title><source>esp@cenet</source><creator>MIYOSHI HIROKAZU ; NISHIMOTO AKIRA ; TAKAHASHI HIRONARI ; NAKAJIMA MORIYOSHI ; ANDOU AKIRA ; MATSUNO YOUKO</creator><creatorcontrib>MIYOSHI HIROKAZU ; NISHIMOTO AKIRA ; TAKAHASHI HIRONARI ; NAKAJIMA MORIYOSHI ; ANDOU AKIRA ; MATSUNO YOUKO</creatorcontrib><description>PURPOSE:To make writing characteristics excellent and to prevent soft writing, by separately arranging a write only transistor, which commonly posseses a floating gate and is easy to write, and a read only transistor, which is hard to write, on one memory cell. CONSTITUTION:A source part 20 is commonly used for both writing and reading. A drain part is divided into a write only part 21 and a read only part 22 by a field oxide silicon film 13. The interval between the source part 20 on the write only side and the drain part 21 is made to be, e.g., as short as about 3.5mum, and electrons are injected. Since a floating gate is in common, the electrons are distributed on the read only side. Meanwhile, the interval between the source part 20 on the read only side is made to be, e.g., as long as about 5mum, and electric field strength between both parts 20 and 22 is made weak. Thus, soft writing can be reduced to the minimum.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>1984</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19840706&DB=EPODOC&CC=JP&NR=S59117270A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19840706&DB=EPODOC&CC=JP&NR=S59117270A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MIYOSHI HIROKAZU</creatorcontrib><creatorcontrib>NISHIMOTO AKIRA</creatorcontrib><creatorcontrib>TAKAHASHI HIRONARI</creatorcontrib><creatorcontrib>NAKAJIMA MORIYOSHI</creatorcontrib><creatorcontrib>ANDOU AKIRA</creatorcontrib><creatorcontrib>MATSUNO YOUKO</creatorcontrib><title>FLOATING GATE TYPE NONVOLATILE MOS SEMICONDUCTOR MEMORY DEVICE</title><description>PURPOSE:To make writing characteristics excellent and to prevent soft writing, by separately arranging a write only transistor, which commonly posseses a floating gate and is easy to write, and a read only transistor, which is hard to write, on one memory cell. CONSTITUTION:A source part 20 is commonly used for both writing and reading. A drain part is divided into a write only part 21 and a read only part 22 by a field oxide silicon film 13. The interval between the source part 20 on the write only side and the drain part 21 is made to be, e.g., as short as about 3.5mum, and electrons are injected. Since a floating gate is in common, the electrons are distributed on the read only side. Meanwhile, the interval between the source part 20 on the read only side is made to be, e.g., as long as about 5mum, and electric field strength between both parts 20 and 22 is made weak. Thus, soft writing can be reduced to the minimum.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1984</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLBz8_F3DPH0c1dwdwxxVQiJDHBV8PP3C_P3AYr6uCr4-gcrBLv6ejr7-7mEOof4Byn4uvr6B0UquLiGeTq78jCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSSeK-AYFNLQ0NzI3MDR2Ni1AAAgN8qtg</recordid><startdate>19840706</startdate><enddate>19840706</enddate><creator>MIYOSHI HIROKAZU</creator><creator>NISHIMOTO AKIRA</creator><creator>TAKAHASHI HIRONARI</creator><creator>NAKAJIMA MORIYOSHI</creator><creator>ANDOU AKIRA</creator><creator>MATSUNO YOUKO</creator><scope>EVB</scope></search><sort><creationdate>19840706</creationdate><title>FLOATING GATE TYPE NONVOLATILE MOS SEMICONDUCTOR MEMORY DEVICE</title><author>MIYOSHI HIROKAZU ; NISHIMOTO AKIRA ; TAKAHASHI HIRONARI ; NAKAJIMA MORIYOSHI ; ANDOU AKIRA ; MATSUNO YOUKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS59117270A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1984</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>MIYOSHI HIROKAZU</creatorcontrib><creatorcontrib>NISHIMOTO AKIRA</creatorcontrib><creatorcontrib>TAKAHASHI HIRONARI</creatorcontrib><creatorcontrib>NAKAJIMA MORIYOSHI</creatorcontrib><creatorcontrib>ANDOU AKIRA</creatorcontrib><creatorcontrib>MATSUNO YOUKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MIYOSHI HIROKAZU</au><au>NISHIMOTO AKIRA</au><au>TAKAHASHI HIRONARI</au><au>NAKAJIMA MORIYOSHI</au><au>ANDOU AKIRA</au><au>MATSUNO YOUKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FLOATING GATE TYPE NONVOLATILE MOS SEMICONDUCTOR MEMORY DEVICE</title><date>1984-07-06</date><risdate>1984</risdate><abstract>PURPOSE:To make writing characteristics excellent and to prevent soft writing, by separately arranging a write only transistor, which commonly posseses a floating gate and is easy to write, and a read only transistor, which is hard to write, on one memory cell. CONSTITUTION:A source part 20 is commonly used for both writing and reading. A drain part is divided into a write only part 21 and a read only part 22 by a field oxide silicon film 13. The interval between the source part 20 on the write only side and the drain part 21 is made to be, e.g., as short as about 3.5mum, and electrons are injected. Since a floating gate is in common, the electrons are distributed on the read only side. Meanwhile, the interval between the source part 20 on the read only side is made to be, e.g., as long as about 5mum, and electric field strength between both parts 20 and 22 is made weak. Thus, soft writing can be reduced to the minimum.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_JPS59117270A |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
title | FLOATING GATE TYPE NONVOLATILE MOS SEMICONDUCTOR MEMORY DEVICE |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-04T21%3A44%3A27IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MIYOSHI%20HIROKAZU&rft.date=1984-07-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPS59117270A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |