SEMICONDUCTOR DEVICE

PURPOSE:To obtain a high performance C-MOS.IC by a method wherein an N channel transistor and a P channel transistor are built in different substrates and the transistors enjoy a roughly equal mobility or the mobility ratio between the two is devised to approach the quantity one. CONSTITUTION:An N t...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: OOSONE TAKASHI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator OOSONE TAKASHI
description PURPOSE:To obtain a high performance C-MOS.IC by a method wherein an N channel transistor and a P channel transistor are built in different substrates and the transistors enjoy a roughly equal mobility or the mobility ratio between the two is devised to approach the quantity one. CONSTITUTION:An N type Ge substrate 22 is selectivity grown on a P type Si substrate 20 by the vapor deposition method. An N channel MOS transistor 21 is built on the substrate 20 and a P channel MOS transistor 23 is built on the substrate 22. Next, source regions 24 and 24' are respectively connected to a ground terminal 25 and a power source terminal 26, drain regions 27 and 27' jointly to an output terminal 29, gate electrodes 28 and 28' jointly to an output terminal 29', constituting an inverter circuit. Mobility is rough balanced between the two transistors, 1,350cm /V.sec for the transistor 21 and 1,900cm /V.sec for the transistor 23. Inductance is also roughly balanced between the two transistors and the gate oxide films can be smaller in area. Parasitic capacity decreases, which results in a high speed switching.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPS57166071A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPS57166071A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPS57166071A3</originalsourceid><addsrcrecordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAcGm5oZmZgbmho7GxKgBAItMHwQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>OOSONE TAKASHI</creator><creatorcontrib>OOSONE TAKASHI</creatorcontrib><description>PURPOSE:To obtain a high performance C-MOS.IC by a method wherein an N channel transistor and a P channel transistor are built in different substrates and the transistors enjoy a roughly equal mobility or the mobility ratio between the two is devised to approach the quantity one. CONSTITUTION:An N type Ge substrate 22 is selectivity grown on a P type Si substrate 20 by the vapor deposition method. An N channel MOS transistor 21 is built on the substrate 20 and a P channel MOS transistor 23 is built on the substrate 22. Next, source regions 24 and 24' are respectively connected to a ground terminal 25 and a power source terminal 26, drain regions 27 and 27' jointly to an output terminal 29, gate electrodes 28 and 28' jointly to an output terminal 29', constituting an inverter circuit. Mobility is rough balanced between the two transistors, 1,350cm /V.sec for the transistor 21 and 1,900cm /V.sec for the transistor 23. Inductance is also roughly balanced between the two transistors and the gate oxide films can be smaller in area. Parasitic capacity decreases, which results in a high speed switching.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1982</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19821013&amp;DB=EPODOC&amp;CC=JP&amp;NR=S57166071A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19821013&amp;DB=EPODOC&amp;CC=JP&amp;NR=S57166071A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OOSONE TAKASHI</creatorcontrib><title>SEMICONDUCTOR DEVICE</title><description>PURPOSE:To obtain a high performance C-MOS.IC by a method wherein an N channel transistor and a P channel transistor are built in different substrates and the transistors enjoy a roughly equal mobility or the mobility ratio between the two is devised to approach the quantity one. CONSTITUTION:An N type Ge substrate 22 is selectivity grown on a P type Si substrate 20 by the vapor deposition method. An N channel MOS transistor 21 is built on the substrate 20 and a P channel MOS transistor 23 is built on the substrate 22. Next, source regions 24 and 24' are respectively connected to a ground terminal 25 and a power source terminal 26, drain regions 27 and 27' jointly to an output terminal 29, gate electrodes 28 and 28' jointly to an output terminal 29', constituting an inverter circuit. Mobility is rough balanced between the two transistors, 1,350cm /V.sec for the transistor 21 and 1,900cm /V.sec for the transistor 23. Inductance is also roughly balanced between the two transistors and the gate oxide films can be smaller in area. Parasitic capacity decreases, which results in a high speed switching.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1982</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAcGm5oZmZgbmho7GxKgBAItMHwQ</recordid><startdate>19821013</startdate><enddate>19821013</enddate><creator>OOSONE TAKASHI</creator><scope>EVB</scope></search><sort><creationdate>19821013</creationdate><title>SEMICONDUCTOR DEVICE</title><author>OOSONE TAKASHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS57166071A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1982</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>OOSONE TAKASHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OOSONE TAKASHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE</title><date>1982-10-13</date><risdate>1982</risdate><abstract>PURPOSE:To obtain a high performance C-MOS.IC by a method wherein an N channel transistor and a P channel transistor are built in different substrates and the transistors enjoy a roughly equal mobility or the mobility ratio between the two is devised to approach the quantity one. CONSTITUTION:An N type Ge substrate 22 is selectivity grown on a P type Si substrate 20 by the vapor deposition method. An N channel MOS transistor 21 is built on the substrate 20 and a P channel MOS transistor 23 is built on the substrate 22. Next, source regions 24 and 24' are respectively connected to a ground terminal 25 and a power source terminal 26, drain regions 27 and 27' jointly to an output terminal 29, gate electrodes 28 and 28' jointly to an output terminal 29', constituting an inverter circuit. Mobility is rough balanced between the two transistors, 1,350cm /V.sec for the transistor 21 and 1,900cm /V.sec for the transistor 23. Inductance is also roughly balanced between the two transistors and the gate oxide films can be smaller in area. Parasitic capacity decreases, which results in a high speed switching.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JPS57166071A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-01T20%3A29%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=OOSONE%20TAKASHI&rft.date=1982-10-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPS57166071A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true