SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
PURPOSE:To obtain a CMOS IC with the effective coexistences of MOS elements for high and low voltage, by forming a plurality of p type well regions with different depths on the main surface of an N type semiconductor substrate with elements mounted on each of regions. CONSTITUTION:A p type impurity...
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creator | OSA YASUNOBU |
description | PURPOSE:To obtain a CMOS IC with the effective coexistences of MOS elements for high and low voltage, by forming a plurality of p type well regions with different depths on the main surface of an N type semiconductor substrate with elements mounted on each of regions. CONSTITUTION:A p type impurity is ion-implanted with an SiO2 film pattern 31 formed on a main surface of the N type substrate 1 as a mask to form the deep well region with depth of approx. 7mum by drive diffusion. Next, another part of the SiO2 film 31 is etched to form the shallow well region with depth of approx. 3mum by ion implantation and drive diffusion. Subsequently, a field SiO2 film 20 is grown with an Si3N4 film 33 as a mask to isolate each of element regions. For the rest, a PMOS is formed on the N type substrate, NMOS for low voltage on the shallow p type well and NMOS for high voltage on the deep p type well to obtain a CMOS IC. |
format | Patent |
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CONSTITUTION:A p type impurity is ion-implanted with an SiO2 film pattern 31 formed on a main surface of the N type substrate 1 as a mask to form the deep well region with depth of approx. 7mum by drive diffusion. Next, another part of the SiO2 film 31 is etched to form the shallow well region with depth of approx. 3mum by ion implantation and drive diffusion. Subsequently, a field SiO2 film 20 is grown with an Si3N4 film 33 as a mask to isolate each of element regions. For the rest, a PMOS is formed on the N type substrate, NMOS for low voltage on the shallow p type well and NMOS for high voltage on the deep p type well to obtain a CMOS IC.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1982</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19820925&DB=EPODOC&CC=JP&NR=S57155768A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19820925&DB=EPODOC&CC=JP&NR=S57155768A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OSA YASUNOBU</creatorcontrib><title>SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE</title><description>PURPOSE:To obtain a CMOS IC with the effective coexistences of MOS elements for high and low voltage, by forming a plurality of p type well regions with different depths on the main surface of an N type semiconductor substrate with elements mounted on each of regions. CONSTITUTION:A p type impurity is ion-implanted with an SiO2 film pattern 31 formed on a main surface of the N type substrate 1 as a mask to form the deep well region with depth of approx. 7mum by drive diffusion. Next, another part of the SiO2 film 31 is etched to form the shallow well region with depth of approx. 3mum by ion implantation and drive diffusion. Subsequently, a field SiO2 film 20 is grown with an Si3N4 film 33 as a mask to isolate each of element regions. For the rest, a PMOS is formed on the N type substrate, NMOS for low voltage on the shallow p type well and NMOS for high voltage on the deep p type well to obtain a CMOS IC.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1982</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAPdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DFFwcQ3zdHblYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxXgHBpuaGpqbmZhaOxsSoAQAF-yRn</recordid><startdate>19820925</startdate><enddate>19820925</enddate><creator>OSA YASUNOBU</creator><scope>EVB</scope></search><sort><creationdate>19820925</creationdate><title>SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE</title><author>OSA YASUNOBU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS57155768A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1982</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>OSA YASUNOBU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OSA YASUNOBU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE</title><date>1982-09-25</date><risdate>1982</risdate><abstract>PURPOSE:To obtain a CMOS IC with the effective coexistences of MOS elements for high and low voltage, by forming a plurality of p type well regions with different depths on the main surface of an N type semiconductor substrate with elements mounted on each of regions. CONSTITUTION:A p type impurity is ion-implanted with an SiO2 film pattern 31 formed on a main surface of the N type substrate 1 as a mask to form the deep well region with depth of approx. 7mum by drive diffusion. Next, another part of the SiO2 film 31 is etched to form the shallow well region with depth of approx. 3mum by ion implantation and drive diffusion. Subsequently, a field SiO2 film 20 is grown with an Si3N4 film 33 as a mask to isolate each of element regions. For the rest, a PMOS is formed on the N type substrate, NMOS for low voltage on the shallow p type well and NMOS for high voltage on the deep p type well to obtain a CMOS IC.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
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