PROCESSING DEVICE

PURPOSE:To simplify an entire processing device, by fixing a specific address line to a specific level at the state that the supply line is opened, in a processor of which sub-storage section is in removable state. CONSTITUTION:When a sub-storage unit 21 is fitted, the level of address lines 9-12 is...

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1. Verfasser:	MAEHARA TOMOHARU
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
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creator	MAEHARA TOMOHARU
description	PURPOSE:To simplify an entire processing device, by fixing a specific address line to a specific level at the state that the supply line is opened, in a processor of which sub-storage section is in removable state. CONSTITUTION:When a sub-storage unit 21 is fitted, the level of address lines 9-12 is determined with signal lines 9'-12', and when a jump instruction JMP6 of a program in a main storage 1 is executed, normal jumping of sub-storage section to an address 6 is excuted. When a sub-storage unit is removed, the signal line 9 is opened and the address line 9 is pulled up with a fixed circuit 4 and fixed to the level 1. When the jump instruction JMP6 is executed, the address jumped to an address 6 in the address space of the main storage 1.
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CONSTITUTION:When a sub-storage unit 21 is fitted, the level of address lines 9-12 is determined with signal lines 9'-12', and when a jump instruction JMP6 of a program in a main storage 1 is executed, normal jumping of sub-storage section to an address 6 is excuted. When a sub-storage unit is removed, the signal line 9 is opened and the address line 9 is pulled up with a fixed circuit 4 and fixed to the level 1. When the jump instruction JMP6 is executed, the address jumped to an address 6 in the address space of the main storage 1.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>1982</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19820717&DB=EPODOC&CC=JP&NR=S57114959A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25544,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19820717&DB=EPODOC&CC=JP&NR=S57114959A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MAEHARA TOMOHARU</creatorcontrib><title>PROCESSING DEVICE</title><description>PURPOSE:To simplify an entire processing device, by fixing a specific address line to a specific level at the state that the supply line is opened, in a processor of which sub-storage section is in removable state. CONSTITUTION:When a sub-storage unit 21 is fitted, the level of address lines 9-12 is determined with signal lines 9'-12', and when a jump instruction JMP6 of a program in a main storage 1 is executed, normal jumping of sub-storage section to an address 6 is excuted. When a sub-storage unit is removed, the signal line 9 is opened and the address line 9 is pulled up with a fixed circuit 4 and fixed to the level 1. When the jump instruction JMP6 is executed, the address jumped to an address 6 in the address space of the main storage 1.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1982</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAMCPJ3dg0O9vRzV3BxDfN0duVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAcGm5oaGJpamlo7GxKgBACzeHi8</recordid><startdate>19820717</startdate><enddate>19820717</enddate><creator>MAEHARA TOMOHARU</creator><scope>EVB</scope></search><sort><creationdate>19820717</creationdate><title>PROCESSING DEVICE</title><author>MAEHARA TOMOHARU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPS57114959A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1982</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>MAEHARA TOMOHARU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MAEHARA TOMOHARU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PROCESSING DEVICE</title><date>1982-07-17</date><risdate>1982</risdate><abstract>PURPOSE:To simplify an entire processing device, by fixing a specific address line to a specific level at the state that the supply line is opened, in a processor of which sub-storage section is in removable state. CONSTITUTION:When a sub-storage unit 21 is fitted, the level of address lines 9-12 is determined with signal lines 9'-12', and when a jump instruction JMP6 of a program in a main storage 1 is executed, normal jumping of sub-storage section to an address 6 is excuted. When a sub-storage unit is removed, the signal line 9 is opened and the address line 9 is pulled up with a fixed circuit 4 and fixed to the level 1. When the jump instruction JMP6 is executed, the address jumped to an address 6 in the address space of the main storage 1.</abstract><oa>free_for_read</oa></addata></record>
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
title	PROCESSING DEVICE
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