SRAM CELL ARRAY AND MANUFACTURE OF THE SAME

PROBLEM TO BE SOLVED: To manufacture a SRAM memory cell whose package density is improved by having it constituted of a word line, a first bit line, a second bit line, a connection line to a first voltage terminal and a connection line to a second voltage terminal as a linear stripe-like structure. SOLUTION: Fifth/sixth transistors are controlled via a word line W, the second source/drain region of the fifth transistor is connected to a first bit line B1, and the second source/drain region of the sixth transistor is connected to a second bit line B2. The first and second bit lines B1 and B2 extend in a direction crossing the word line W. First to fourth transistors are arranged at the corners of a square and the corners, where the first and fourth transistors are arranged to face each other on a diagonal line. The third transistor is arranged between the first and fifth transistors, and the second transistor between the fourth and sixth transistors.