SENSE AMPLIFIER CIRCUIT
PROBLEM TO BE SOLVED: To obtain a sense amplifier circuit free from read errors due to the power supply noise. SOLUTION: A clock generator circuit 14 outputs a transfer gate control signal after receiving an output ENABLE signal from a DELAY circuit 12. Upon receipt of the transfer gate control sign...
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| creator | DEGUCHI YASUSHI |
| description | PROBLEM TO BE SOLVED: To obtain a sense amplifier circuit free from read errors due to the power supply noise. SOLUTION: A clock generator circuit 14 outputs a transfer gate control signal after receiving an output ENABLE signal from a DELAY circuit 12. Upon receipt of the transfer gate control signal from the clock generator circuit 14 a sense amplifier 15 turns off the transfer gate. Upon receipt of the output ENABLE signal from an address input-ATD circuit 11-DELAY circuit 12 an output buffer 13 controls the data output according to this ENABLE signal. If the turn off of the transfer gate is effected during the time for which the output power noise is being produced, the power noise influence can be suppressed. Thus, it is possible to avoid a read error due to the influence of the output power noise of the sense amplifier. |
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Upon receipt of the transfer gate control signal from the clock generator circuit 14 a sense amplifier 15 turns off the transfer gate. Upon receipt of the output ENABLE signal from an address input-ATD circuit 11-DELAY circuit 12 an output buffer 13 controls the data output according to this ENABLE signal. If the turn off of the transfer gate is effected during the time for which the output power noise is being produced, the power noise influence can be suppressed. Thus, it is possible to avoid a read error due to the influence of the output power noise of the sense amplifier.</description><edition>6</edition><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>1999</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19990618&DB=EPODOC&CC=JP&NR=H11162177A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19990618&DB=EPODOC&CC=JP&NR=H11162177A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DEGUCHI YASUSHI</creatorcontrib><title>SENSE AMPLIFIER CIRCUIT</title><description>PROBLEM TO BE SOLVED: To obtain a sense amplifier circuit free from read errors due to the power supply noise. SOLUTION: A clock generator circuit 14 outputs a transfer gate control signal after receiving an output ENABLE signal from a DELAY circuit 12. Upon receipt of the transfer gate control signal from the clock generator circuit 14 a sense amplifier 15 turns off the transfer gate. Upon receipt of the output ENABLE signal from an address input-ATD circuit 11-DELAY circuit 12 an output buffer 13 controls the data output according to this ENABLE signal. If the turn off of the transfer gate is effected during the time for which the output power noise is being produced, the power noise influence can be suppressed. Thus, it is possible to avoid a read error due to the influence of the output power noise of the sense amplifier.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1999</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAPdvULdlVw9A3w8XTzdA1ScPYMcg71DOFhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAR6GhoZmRobm5o7GxKgBANi7H54</recordid><startdate>19990618</startdate><enddate>19990618</enddate><creator>DEGUCHI YASUSHI</creator><scope>EVB</scope></search><sort><creationdate>19990618</creationdate><title>SENSE AMPLIFIER CIRCUIT</title><author>DEGUCHI YASUSHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH11162177A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1999</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>DEGUCHI YASUSHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DEGUCHI YASUSHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SENSE AMPLIFIER CIRCUIT</title><date>1999-06-18</date><risdate>1999</risdate><abstract>PROBLEM TO BE SOLVED: To obtain a sense amplifier circuit free from read errors due to the power supply noise. SOLUTION: A clock generator circuit 14 outputs a transfer gate control signal after receiving an output ENABLE signal from a DELAY circuit 12. Upon receipt of the transfer gate control signal from the clock generator circuit 14 a sense amplifier 15 turns off the transfer gate. Upon receipt of the output ENABLE signal from an address input-ATD circuit 11-DELAY circuit 12 an output buffer 13 controls the data output according to this ENABLE signal. If the turn off of the transfer gate is effected during the time for which the output power noise is being produced, the power noise influence can be suppressed. Thus, it is possible to avoid a read error due to the influence of the output power noise of the sense amplifier.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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| title | SENSE AMPLIFIER CIRCUIT |
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