ELECTRIC DEVICE AND MANUFACTURE THEREOF

PROBLEM TO BE SOLVED: To enable a dielectric structure to be formed inside a non-planar capacitor and a ferroelectric memory cell by a method wherein a recess where a dielectric is deposited is demarcated by a gap between a plate electrode and a stacked electrode. SOLUTION: A capacitor structure 100...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: DAVID EDWARD KOTTEKI, ALFRED GRILL, JAMES HARTFIEL COMFORT, CATHERINE LYNN SANGER, LAUR EDMUND ACOSTA
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator DAVID EDWARD KOTTEKI
ALFRED GRILL
JAMES HARTFIEL COMFORT
CATHERINE LYNN SANGER
LAUR EDMUND ACOSTA
description PROBLEM TO BE SOLVED: To enable a dielectric structure to be formed inside a non-planar capacitor and a ferroelectric memory cell by a method wherein a recess where a dielectric is deposited is demarcated by a gap between a plate electrode and a stacked electrode. SOLUTION: A capacitor structure 100 is composed of a first electrode or a plate electrode 1 and a second electrode or a stacked electrode 2 surrounded with the plate electrode 1. The plate electrode 1 is isolated from the stacked electrode 2 by a narrow gap filled with a capacitor dielectric body 3. A conductive plug 4 buried in a dielectric body 5 is brought into contact with a conductive region 6 on a board 20. A gap can be formed between the plate electrode 1 and the stacked electrode 2 in a final structure or between one or more sacrifice materials and either the plate electrode 1 or the stacked electrode 2. By this setup, the dielectric body 3 is not required to be deposited through a conformal process such as a chemical vapor deposition method.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH1041474A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH1041474A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH1041474A3</originalsourceid><addsrcrecordid>eNrjZFB39XF1DgnydFZwcQ3zdHZVcPRzUfB19At1c3QOCQ1yVQjxcA1y9XfjYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxXgEehgYmhibmJo7GRCgBAJJ4I24</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ELECTRIC DEVICE AND MANUFACTURE THEREOF</title><source>esp@cenet</source><creator>DAVID EDWARD KOTTEKI ; ALFRED GRILL ; JAMES HARTFIEL COMFORT ; CATHERINE LYNN SANGER ; LAUR EDMUND ACOSTA</creator><creatorcontrib>DAVID EDWARD KOTTEKI ; ALFRED GRILL ; JAMES HARTFIEL COMFORT ; CATHERINE LYNN SANGER ; LAUR EDMUND ACOSTA</creatorcontrib><description>PROBLEM TO BE SOLVED: To enable a dielectric structure to be formed inside a non-planar capacitor and a ferroelectric memory cell by a method wherein a recess where a dielectric is deposited is demarcated by a gap between a plate electrode and a stacked electrode. SOLUTION: A capacitor structure 100 is composed of a first electrode or a plate electrode 1 and a second electrode or a stacked electrode 2 surrounded with the plate electrode 1. The plate electrode 1 is isolated from the stacked electrode 2 by a narrow gap filled with a capacitor dielectric body 3. A conductive plug 4 buried in a dielectric body 5 is brought into contact with a conductive region 6 on a board 20. A gap can be formed between the plate electrode 1 and the stacked electrode 2 in a final structure or between one or more sacrifice materials and either the plate electrode 1 or the stacked electrode 2. By this setup, the dielectric body 3 is not required to be deposited through a conformal process such as a chemical vapor deposition method.</description><edition>6</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1998</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19980213&amp;DB=EPODOC&amp;CC=JP&amp;NR=H1041474A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19980213&amp;DB=EPODOC&amp;CC=JP&amp;NR=H1041474A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DAVID EDWARD KOTTEKI</creatorcontrib><creatorcontrib>ALFRED GRILL</creatorcontrib><creatorcontrib>JAMES HARTFIEL COMFORT</creatorcontrib><creatorcontrib>CATHERINE LYNN SANGER</creatorcontrib><creatorcontrib>LAUR EDMUND ACOSTA</creatorcontrib><title>ELECTRIC DEVICE AND MANUFACTURE THEREOF</title><description>PROBLEM TO BE SOLVED: To enable a dielectric structure to be formed inside a non-planar capacitor and a ferroelectric memory cell by a method wherein a recess where a dielectric is deposited is demarcated by a gap between a plate electrode and a stacked electrode. SOLUTION: A capacitor structure 100 is composed of a first electrode or a plate electrode 1 and a second electrode or a stacked electrode 2 surrounded with the plate electrode 1. The plate electrode 1 is isolated from the stacked electrode 2 by a narrow gap filled with a capacitor dielectric body 3. A conductive plug 4 buried in a dielectric body 5 is brought into contact with a conductive region 6 on a board 20. A gap can be formed between the plate electrode 1 and the stacked electrode 2 in a final structure or between one or more sacrifice materials and either the plate electrode 1 or the stacked electrode 2. By this setup, the dielectric body 3 is not required to be deposited through a conformal process such as a chemical vapor deposition method.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1998</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFB39XF1DgnydFZwcQ3zdHZVcPRzUfB19At1c3QOCQ1yVQjxcA1y9XfjYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxXgEehgYmhibmJo7GRCgBAJJ4I24</recordid><startdate>19980213</startdate><enddate>19980213</enddate><creator>DAVID EDWARD KOTTEKI</creator><creator>ALFRED GRILL</creator><creator>JAMES HARTFIEL COMFORT</creator><creator>CATHERINE LYNN SANGER</creator><creator>LAUR EDMUND ACOSTA</creator><scope>EVB</scope></search><sort><creationdate>19980213</creationdate><title>ELECTRIC DEVICE AND MANUFACTURE THEREOF</title><author>DAVID EDWARD KOTTEKI ; ALFRED GRILL ; JAMES HARTFIEL COMFORT ; CATHERINE LYNN SANGER ; LAUR EDMUND ACOSTA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH1041474A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1998</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>DAVID EDWARD KOTTEKI</creatorcontrib><creatorcontrib>ALFRED GRILL</creatorcontrib><creatorcontrib>JAMES HARTFIEL COMFORT</creatorcontrib><creatorcontrib>CATHERINE LYNN SANGER</creatorcontrib><creatorcontrib>LAUR EDMUND ACOSTA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DAVID EDWARD KOTTEKI</au><au>ALFRED GRILL</au><au>JAMES HARTFIEL COMFORT</au><au>CATHERINE LYNN SANGER</au><au>LAUR EDMUND ACOSTA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ELECTRIC DEVICE AND MANUFACTURE THEREOF</title><date>1998-02-13</date><risdate>1998</risdate><abstract>PROBLEM TO BE SOLVED: To enable a dielectric structure to be formed inside a non-planar capacitor and a ferroelectric memory cell by a method wherein a recess where a dielectric is deposited is demarcated by a gap between a plate electrode and a stacked electrode. SOLUTION: A capacitor structure 100 is composed of a first electrode or a plate electrode 1 and a second electrode or a stacked electrode 2 surrounded with the plate electrode 1. The plate electrode 1 is isolated from the stacked electrode 2 by a narrow gap filled with a capacitor dielectric body 3. A conductive plug 4 buried in a dielectric body 5 is brought into contact with a conductive region 6 on a board 20. A gap can be formed between the plate electrode 1 and the stacked electrode 2 in a final structure or between one or more sacrifice materials and either the plate electrode 1 or the stacked electrode 2. By this setup, the dielectric body 3 is not required to be deposited through a conformal process such as a chemical vapor deposition method.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JPH1041474A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title ELECTRIC DEVICE AND MANUFACTURE THEREOF
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T18%3A48%3A20IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=DAVID%20EDWARD%20KOTTEKI&rft.date=1998-02-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPH1041474A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true