METHOD FOR FORMATION OF MULTILAYER INTERCONNECTION IN SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To prevent a thick patterning layer from being formed in a step part by a method wherein a third insulating film and a fourth insulating film are etched, a via hole which exposes a lower-part conductive film pattern is formed and an upper-part conductive film pattern which come...

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Bibliographische Detailangaben
Hauptverfasser: PARK YOUNG-HUN, CHO SHOGEN, KIN SHAKUTAI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To prevent a thick patterning layer from being formed in a step part by a method wherein a third insulating film and a fourth insulating film are etched, a via hole which exposes a lower-part conductive film pattern is formed and an upper-part conductive film pattern which comes into contact with the lower-part conductive film pattern through the via hole is formed. SOLUTION: A third insulating film 160 whose thickness is uniform is formed on the whole face on which lower-part conductive film patterns 150a, 150b are formed, an SOG film 170 is formed on it, the whole face is etched back uniformly, and a flattening layer 170a is formed. Then, a fourth insulating film 180 is formed on the flattening layer 170a, the fourth insulating film 180 and the third insulating film 160 are etched sequentially, and a fourth insulating film pattern 180 and a third insulating film pattern 160a which are provided with via holes used to expose the lower-part conductive film patterns 150a, 150b are formed. In addition, upper-part conductive film patterns 190a, 190b which come into contact with the lower-part conductive film patterns 150a, 150b are formed on the fourth insulating film pattern 180.