METHOD FOR MANUFACTURING HIGH-CAPACITANCE STORAGE NODE STRUCTURE IN SUBSTRATE AND SUBSTRATE HAVING HIGH-CAPACITANCE STORAGE NODE
PROBLEM TO BE SOLVED: To provide a simple method for manufacturing the high-capacitance storage node structure of a DRAM(dynamic random access memory), etc. SOLUTION: In order to form a high-capacitance storage node structure in a substrate 10, a negative resist area 16 and a positive resist area 18...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | MARK C HEIKEE WILLIAM H MA DAVID V HOLICK STEPHEN J HORMES |
| description | PROBLEM TO BE SOLVED: To provide a simple method for manufacturing the high-capacitance storage node structure of a DRAM(dynamic random access memory), etc. SOLUTION: In order to form a high-capacitance storage node structure in a substrate 10, a negative resist area 16 and a positive resist area 18 are formed in an exposed area 14 by patterning a hybrid resist 12. After the positive resist area 18 is removed, the substrate 10 is etched by using the non-exposed part of the hybrid resist 12 and the negative resist area 16 as masks. As a result, a trench 22 and a projecting section 24 which is positioned at the center of the trench 22 and projects upward are formed in the substrate 10. Then, a capacitor 26 is formed by coating the side wall of the trench 22 and the projecting section 24 with a dielectric material 28 and filling up the trench 22 with a conductive material 30. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH10154796A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH10154796A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH10154796A3</originalsourceid><addsrcrecordid>eNrjZGjwdQ3x8HdRcPMPUvB19At1c3QOCQ3y9HNX8PB099B1dgxwdPYMcfRzdlUIDvEPcnR3VfDzdwFxgkJBKl0VPP0UgkOdgHzHEFcFRz8XJJ6HYxhBk3gYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSbxXgIehgaGpibmlmaMxMWoAiMs8gQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD FOR MANUFACTURING HIGH-CAPACITANCE STORAGE NODE STRUCTURE IN SUBSTRATE AND SUBSTRATE HAVING HIGH-CAPACITANCE STORAGE NODE</title><source>esp@cenet</source><creator>MARK C HEIKEE ; WILLIAM H MA ; DAVID V HOLICK ; STEPHEN J HORMES</creator><creatorcontrib>MARK C HEIKEE ; WILLIAM H MA ; DAVID V HOLICK ; STEPHEN J HORMES</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a simple method for manufacturing the high-capacitance storage node structure of a DRAM(dynamic random access memory), etc. SOLUTION: In order to form a high-capacitance storage node structure in a substrate 10, a negative resist area 16 and a positive resist area 18 are formed in an exposed area 14 by patterning a hybrid resist 12. After the positive resist area 18 is removed, the substrate 10 is etched by using the non-exposed part of the hybrid resist 12 and the negative resist area 16 as masks. As a result, a trench 22 and a projecting section 24 which is positioned at the center of the trench 22 and projects upward are formed in the substrate 10. Then, a capacitor 26 is formed by coating the side wall of the trench 22 and the projecting section 24 with a dielectric material 28 and filling up the trench 22 with a conductive material 30.</description><edition>6</edition><language>eng</language><subject>APPARATUS SPECIALLY ADAPTED THEREFOR ; BASIC ELECTRIC ELEMENTS ; CINEMATOGRAPHY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; ELECTROGRAPHY ; HOLOGRAPHY ; MATERIALS THEREFOR ; ORIGINALS THEREFOR ; PHOTOGRAPHY ; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>1998</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19980609&DB=EPODOC&CC=JP&NR=H10154796A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19980609&DB=EPODOC&CC=JP&NR=H10154796A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MARK C HEIKEE</creatorcontrib><creatorcontrib>WILLIAM H MA</creatorcontrib><creatorcontrib>DAVID V HOLICK</creatorcontrib><creatorcontrib>STEPHEN J HORMES</creatorcontrib><title>METHOD FOR MANUFACTURING HIGH-CAPACITANCE STORAGE NODE STRUCTURE IN SUBSTRATE AND SUBSTRATE HAVING HIGH-CAPACITANCE STORAGE NODE</title><description>PROBLEM TO BE SOLVED: To provide a simple method for manufacturing the high-capacitance storage node structure of a DRAM(dynamic random access memory), etc. SOLUTION: In order to form a high-capacitance storage node structure in a substrate 10, a negative resist area 16 and a positive resist area 18 are formed in an exposed area 14 by patterning a hybrid resist 12. After the positive resist area 18 is removed, the substrate 10 is etched by using the non-exposed part of the hybrid resist 12 and the negative resist area 16 as masks. As a result, a trench 22 and a projecting section 24 which is positioned at the center of the trench 22 and projects upward are formed in the substrate 10. Then, a capacitor 26 is formed by coating the side wall of the trench 22 and the projecting section 24 with a dielectric material 28 and filling up the trench 22 with a conductive material 30.</description><subject>APPARATUS SPECIALLY ADAPTED THEREFOR</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CINEMATOGRAPHY</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>ELECTROGRAPHY</subject><subject>HOLOGRAPHY</subject><subject>MATERIALS THEREFOR</subject><subject>ORIGINALS THEREFOR</subject><subject>PHOTOGRAPHY</subject><subject>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1998</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZGjwdQ3x8HdRcPMPUvB19At1c3QOCQ3y9HNX8PB099B1dgxwdPYMcfRzdlUIDvEPcnR3VfDzdwFxgkJBKl0VPP0UgkOdgHzHEFcFRz8XJJ6HYxhBk3gYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSbxXgIehgaGpibmlmaMxMWoAiMs8gQ</recordid><startdate>19980609</startdate><enddate>19980609</enddate><creator>MARK C HEIKEE</creator><creator>WILLIAM H MA</creator><creator>DAVID V HOLICK</creator><creator>STEPHEN J HORMES</creator><scope>EVB</scope></search><sort><creationdate>19980609</creationdate><title>METHOD FOR MANUFACTURING HIGH-CAPACITANCE STORAGE NODE STRUCTURE IN SUBSTRATE AND SUBSTRATE HAVING HIGH-CAPACITANCE STORAGE NODE</title><author>MARK C HEIKEE ; WILLIAM H MA ; DAVID V HOLICK ; STEPHEN J HORMES</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH10154796A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1998</creationdate><topic>APPARATUS SPECIALLY ADAPTED THEREFOR</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CINEMATOGRAPHY</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>ELECTROGRAPHY</topic><topic>HOLOGRAPHY</topic><topic>MATERIALS THEREFOR</topic><topic>ORIGINALS THEREFOR</topic><topic>PHOTOGRAPHY</topic><topic>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MARK C HEIKEE</creatorcontrib><creatorcontrib>WILLIAM H MA</creatorcontrib><creatorcontrib>DAVID V HOLICK</creatorcontrib><creatorcontrib>STEPHEN J HORMES</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MARK C HEIKEE</au><au>WILLIAM H MA</au><au>DAVID V HOLICK</au><au>STEPHEN J HORMES</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR MANUFACTURING HIGH-CAPACITANCE STORAGE NODE STRUCTURE IN SUBSTRATE AND SUBSTRATE HAVING HIGH-CAPACITANCE STORAGE NODE</title><date>1998-06-09</date><risdate>1998</risdate><abstract>PROBLEM TO BE SOLVED: To provide a simple method for manufacturing the high-capacitance storage node structure of a DRAM(dynamic random access memory), etc. SOLUTION: In order to form a high-capacitance storage node structure in a substrate 10, a negative resist area 16 and a positive resist area 18 are formed in an exposed area 14 by patterning a hybrid resist 12. After the positive resist area 18 is removed, the substrate 10 is etched by using the non-exposed part of the hybrid resist 12 and the negative resist area 16 as masks. As a result, a trench 22 and a projecting section 24 which is positioned at the center of the trench 22 and projects upward are formed in the substrate 10. Then, a capacitor 26 is formed by coating the side wall of the trench 22 and the projecting section 24 with a dielectric material 28 and filling up the trench 22 with a conductive material 30.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_JPH10154796A |
| source | esp@cenet |
| subjects | APPARATUS SPECIALLY ADAPTED THEREFOR BASIC ELECTRIC ELEMENTS CINEMATOGRAPHY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY ELECTROGRAPHY HOLOGRAPHY MATERIALS THEREFOR ORIGINALS THEREFOR PHOTOGRAPHY PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES PHYSICS SEMICONDUCTOR DEVICES |
| title | METHOD FOR MANUFACTURING HIGH-CAPACITANCE STORAGE NODE STRUCTURE IN SUBSTRATE AND SUBSTRATE HAVING HIGH-CAPACITANCE STORAGE NODE |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T14%3A13%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MARK%20C%20HEIKEE&rft.date=1998-06-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPH10154796A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |