MANUFACTURE OF SEMICONDUCTOR DEVICE

MANUFACTURE OF SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a manufacturing method capable of suppressing halation during lithography process and forming connection hole exactly as designed regarding a semiconductor device having connection holes formed crossing between different lower layer wiring. SOLUTION: A gate electrode...

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1. Verfasser: KUROKAWA ATSUO
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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description PROBLEM TO BE SOLVED: To provide a manufacturing method capable of suppressing halation during lithography process and forming connection hole exactly as designed regarding a semiconductor device having connection holes formed crossing between different lower layer wiring. SOLUTION: A gate electrode and the first wiring layer 8 are formed on a gate film oxide 6 on a Si substrate 2, high concentration diffusion 14 is formed on the Si substrate 2, and a film (reflection protective film) 16 made from the Si3 N4 base is formed. An interlayer insulation film 18, the second wiring layer 22, and interlayer insulation film 24 are formed on it and an opening 28 is formed on the resist 26 by lithography technology. A connection hole is formed by an anisotropic etching in the bottom of the opening 28. Halation caused by lithography light is suppressed by the Si3 N4 based film 16 and the opening 28 (connection hole) can be formed exactly as designed.
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SOLUTION: A gate electrode and the first wiring layer 8 are formed on a gate film oxide 6 on a Si substrate 2, high concentration diffusion 14 is formed on the Si substrate 2, and a film (reflection protective film) 16 made from the Si3 N4 base is formed. An interlayer insulation film 18, the second wiring layer 22, and interlayer insulation film 24 are formed on it and an opening 28 is formed on the resist 26 by lithography technology. A connection hole is formed by an anisotropic etching in the bottom of the opening 28. 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SOLUTION: A gate electrode and the first wiring layer 8 are formed on a gate film oxide 6 on a Si substrate 2, high concentration diffusion 14 is formed on the Si substrate 2, and a film (reflection protective film) 16 made from the Si3 N4 base is formed. An interlayer insulation film 18, the second wiring layer 22, and interlayer insulation film 24 are formed on it and an opening 28 is formed on the resist 26 by lithography technology. A connection hole is formed by an anisotropic etching in the bottom of the opening 28. Halation caused by lithography light is suppressed by the Si3 N4 based film 16 and the opening 28 (connection hole) can be formed exactly as designed.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title MANUFACTURE OF SEMICONDUCTOR DEVICE
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