MANUFACTURE OF SEMICONDUCTOR DEVICE
PROBLEM TO BE SOLVED: To obtain a semiconductor device which eliminates a cause obstructing the performance of a high-speed operation when a bipolar transistor is formed, in with the performance of the high-speed operation of every transistor is not different when, e.g. the effective emitter size of...
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creator | SHINOHARA MAMORU |
description | PROBLEM TO BE SOLVED: To obtain a semiconductor device which eliminates a cause obstructing the performance of a high-speed operation when a bipolar transistor is formed, in with the performance of the high-speed operation of every transistor is not different when, e.g. the effective emitter size of one transistor becomes larger than the effective emitter size of the other and in which a MIS(metal insulation silicon) capacitance is formed simultaneously without largely increasing a process. SOLUTION: In the manufacturing method of a semiconductor device which comprises a bipolar transistor and a MIS capacitance element, insulating films 7 which are composed of SiO2 , SiN or the like are formed in the base formation region and the MIS capacitance III formation region of at least a bipolar transistor II on the surface of a semiconductor substrate, the insulating film 7 at least on an emitter formation region is removed, and conductors 8', 8" which are composed of poly-Si are formed in arbitrary regions on the surface of the semiconductor substrate in such a way that at least the region in which the insulating film is removed and the MIS capacitance formation region are included. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH09232439A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH09232439A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH09232439A3</originalsourceid><addsrcrecordid>eNrjZFD2dfQLdXN0DgkNclXwd1MIdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAR4GlkbGRibGlo7GxKgBAGp3Iws</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MANUFACTURE OF SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>SHINOHARA MAMORU</creator><creatorcontrib>SHINOHARA MAMORU</creatorcontrib><description>PROBLEM TO BE SOLVED: To obtain a semiconductor device which eliminates a cause obstructing the performance of a high-speed operation when a bipolar transistor is formed, in with the performance of the high-speed operation of every transistor is not different when, e.g. the effective emitter size of one transistor becomes larger than the effective emitter size of the other and in which a MIS(metal insulation silicon) capacitance is formed simultaneously without largely increasing a process. SOLUTION: In the manufacturing method of a semiconductor device which comprises a bipolar transistor and a MIS capacitance element, insulating films 7 which are composed of SiO2 , SiN or the like are formed in the base formation region and the MIS capacitance III formation region of at least a bipolar transistor II on the surface of a semiconductor substrate, the insulating film 7 at least on an emitter formation region is removed, and conductors 8', 8" which are composed of poly-Si are formed in arbitrary regions on the surface of the semiconductor substrate in such a way that at least the region in which the insulating film is removed and the MIS capacitance formation region are included.</description><edition>6</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1997</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19970905&DB=EPODOC&CC=JP&NR=H09232439A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19970905&DB=EPODOC&CC=JP&NR=H09232439A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHINOHARA MAMORU</creatorcontrib><title>MANUFACTURE OF SEMICONDUCTOR DEVICE</title><description>PROBLEM TO BE SOLVED: To obtain a semiconductor device which eliminates a cause obstructing the performance of a high-speed operation when a bipolar transistor is formed, in with the performance of the high-speed operation of every transistor is not different when, e.g. the effective emitter size of one transistor becomes larger than the effective emitter size of the other and in which a MIS(metal insulation silicon) capacitance is formed simultaneously without largely increasing a process. SOLUTION: In the manufacturing method of a semiconductor device which comprises a bipolar transistor and a MIS capacitance element, insulating films 7 which are composed of SiO2 , SiN or the like are formed in the base formation region and the MIS capacitance III formation region of at least a bipolar transistor II on the surface of a semiconductor substrate, the insulating film 7 at least on an emitter formation region is removed, and conductors 8', 8" which are composed of poly-Si are formed in arbitrary regions on the surface of the semiconductor substrate in such a way that at least the region in which the insulating film is removed and the MIS capacitance formation region are included.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1997</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFD2dfQLdXN0DgkNclXwd1MIdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAR4GlkbGRibGlo7GxKgBAGp3Iws</recordid><startdate>19970905</startdate><enddate>19970905</enddate><creator>SHINOHARA MAMORU</creator><scope>EVB</scope></search><sort><creationdate>19970905</creationdate><title>MANUFACTURE OF SEMICONDUCTOR DEVICE</title><author>SHINOHARA MAMORU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH09232439A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1997</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SHINOHARA MAMORU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHINOHARA MAMORU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MANUFACTURE OF SEMICONDUCTOR DEVICE</title><date>1997-09-05</date><risdate>1997</risdate><abstract>PROBLEM TO BE SOLVED: To obtain a semiconductor device which eliminates a cause obstructing the performance of a high-speed operation when a bipolar transistor is formed, in with the performance of the high-speed operation of every transistor is not different when, e.g. the effective emitter size of one transistor becomes larger than the effective emitter size of the other and in which a MIS(metal insulation silicon) capacitance is formed simultaneously without largely increasing a process. SOLUTION: In the manufacturing method of a semiconductor device which comprises a bipolar transistor and a MIS capacitance element, insulating films 7 which are composed of SiO2 , SiN or the like are formed in the base formation region and the MIS capacitance III formation region of at least a bipolar transistor II on the surface of a semiconductor substrate, the insulating film 7 at least on an emitter formation region is removed, and conductors 8', 8" which are composed of poly-Si are formed in arbitrary regions on the surface of the semiconductor substrate in such a way that at least the region in which the insulating film is removed and the MIS capacitance formation region are included.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | MANUFACTURE OF SEMICONDUCTOR DEVICE |
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