BURN-IN TEST METHOD FOR SEMICONDUCTOR MEMORY DEVICE AND CONTROL CIRCUIT FOR BURN-IN TIMING FOR IT
PROBLEM TO BE SOLVED: To prevent an overcurrent capable of being generated at the time of a burn-in by a method wherein burn-in control signals transmitted to each decoder in a first process are transmitted to each decoder and burnt in, and the control signals are inverted and brought to an on state...
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creator | KEN KOKUKAN BOKU KITETSU |
description | PROBLEM TO BE SOLVED: To prevent an overcurrent capable of being generated at the time of a burn-in by a method wherein burn-in control signals transmitted to each decoder in a first process are transmitted to each decoder and burnt in, and the control signals are inverted and brought to an on state after a fixed time. SOLUTION: When a BIN control signal BI as an output signal from a burn-in BIN control circuit 100 is changed from L to H, a mode is converted from a normal mode to a BIN mode, a signal at that time is not delayed and is transmitted to a pre-charge section 104 as a BIN control signal BI', and clamp Trs 105A, 105B are turned off. On the other hand, a complementary BIN control signal BIB converting a column signal Y into the BIN mode is transmitted after the delay of a delay circuit 113 in a low signal XW. Accordingly, the signal XW or the signal Y is made later than the Trs 105A, 105B and enters into the BIN mode, and the path of an overcurrent is formed. When a device in the BIN mode is converted into the normal mode, the signal BI is changed from H to L, the complementary BIN control signal BIB is transferred instantaneously without through a delay circuit 114, and the signal XW or Y is altered into the normal mode. On the other hand, the BIN control signal BI' is generated through the circuit 113, and changes the Trs 105A, 105B from the BIN mode to the normal mode. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH09120697A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH09120697A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH09120697A3</originalsourceid><addsrcrecordid>eNrjZEh0Cg3y0_X0UwhxDQ5R8HUN8fB3UXDzD1IIdvX1dPb3cwl1DgHyfF19_YMiFVxcwzydXRUc_VwUgHIhQf4-Cs6eQc6hniFgPXCzPH09_dzBQp4hPAysaYk5xam8UJqbQdHNNcTZQze1ID8-tbggMTk1L7Uk3ivAw8DS0MjAzNLc0ZgYNQCtOTPO</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>BURN-IN TEST METHOD FOR SEMICONDUCTOR MEMORY DEVICE AND CONTROL CIRCUIT FOR BURN-IN TIMING FOR IT</title><source>esp@cenet</source><creator>KEN KOKUKAN ; BOKU KITETSU</creator><creatorcontrib>KEN KOKUKAN ; BOKU KITETSU</creatorcontrib><description>PROBLEM TO BE SOLVED: To prevent an overcurrent capable of being generated at the time of a burn-in by a method wherein burn-in control signals transmitted to each decoder in a first process are transmitted to each decoder and burnt in, and the control signals are inverted and brought to an on state after a fixed time. SOLUTION: When a BIN control signal BI as an output signal from a burn-in BIN control circuit 100 is changed from L to H, a mode is converted from a normal mode to a BIN mode, a signal at that time is not delayed and is transmitted to a pre-charge section 104 as a BIN control signal BI', and clamp Trs 105A, 105B are turned off. On the other hand, a complementary BIN control signal BIB converting a column signal Y into the BIN mode is transmitted after the delay of a delay circuit 113 in a low signal XW. Accordingly, the signal XW or the signal Y is made later than the Trs 105A, 105B and enters into the BIN mode, and the path of an overcurrent is formed. When a device in the BIN mode is converted into the normal mode, the signal BI is changed from H to L, the complementary BIN control signal BIB is transferred instantaneously without through a delay circuit 114, and the signal XW or Y is altered into the normal mode. On the other hand, the BIN control signal BI' is generated through the circuit 113, and changes the Trs 105A, 105B from the BIN mode to the normal mode.</description><edition>6</edition><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>1997</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19970506&DB=EPODOC&CC=JP&NR=H09120697A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19970506&DB=EPODOC&CC=JP&NR=H09120697A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KEN KOKUKAN</creatorcontrib><creatorcontrib>BOKU KITETSU</creatorcontrib><title>BURN-IN TEST METHOD FOR SEMICONDUCTOR MEMORY DEVICE AND CONTROL CIRCUIT FOR BURN-IN TIMING FOR IT</title><description>PROBLEM TO BE SOLVED: To prevent an overcurrent capable of being generated at the time of a burn-in by a method wherein burn-in control signals transmitted to each decoder in a first process are transmitted to each decoder and burnt in, and the control signals are inverted and brought to an on state after a fixed time. SOLUTION: When a BIN control signal BI as an output signal from a burn-in BIN control circuit 100 is changed from L to H, a mode is converted from a normal mode to a BIN mode, a signal at that time is not delayed and is transmitted to a pre-charge section 104 as a BIN control signal BI', and clamp Trs 105A, 105B are turned off. On the other hand, a complementary BIN control signal BIB converting a column signal Y into the BIN mode is transmitted after the delay of a delay circuit 113 in a low signal XW. Accordingly, the signal XW or the signal Y is made later than the Trs 105A, 105B and enters into the BIN mode, and the path of an overcurrent is formed. When a device in the BIN mode is converted into the normal mode, the signal BI is changed from H to L, the complementary BIN control signal BIB is transferred instantaneously without through a delay circuit 114, and the signal XW or Y is altered into the normal mode. On the other hand, the BIN control signal BI' is generated through the circuit 113, and changes the Trs 105A, 105B from the BIN mode to the normal mode.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1997</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZEh0Cg3y0_X0UwhxDQ5R8HUN8fB3UXDzD1IIdvX1dPb3cwl1DgHyfF19_YMiFVxcwzydXRUc_VwUgHIhQf4-Cs6eQc6hniFgPXCzPH09_dzBQp4hPAysaYk5xam8UJqbQdHNNcTZQze1ID8-tbggMTk1L7Uk3ivAw8DS0MjAzNLc0ZgYNQCtOTPO</recordid><startdate>19970506</startdate><enddate>19970506</enddate><creator>KEN KOKUKAN</creator><creator>BOKU KITETSU</creator><scope>EVB</scope></search><sort><creationdate>19970506</creationdate><title>BURN-IN TEST METHOD FOR SEMICONDUCTOR MEMORY DEVICE AND CONTROL CIRCUIT FOR BURN-IN TIMING FOR IT</title><author>KEN KOKUKAN ; BOKU KITETSU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH09120697A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1997</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>KEN KOKUKAN</creatorcontrib><creatorcontrib>BOKU KITETSU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KEN KOKUKAN</au><au>BOKU KITETSU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>BURN-IN TEST METHOD FOR SEMICONDUCTOR MEMORY DEVICE AND CONTROL CIRCUIT FOR BURN-IN TIMING FOR IT</title><date>1997-05-06</date><risdate>1997</risdate><abstract>PROBLEM TO BE SOLVED: To prevent an overcurrent capable of being generated at the time of a burn-in by a method wherein burn-in control signals transmitted to each decoder in a first process are transmitted to each decoder and burnt in, and the control signals are inverted and brought to an on state after a fixed time. SOLUTION: When a BIN control signal BI as an output signal from a burn-in BIN control circuit 100 is changed from L to H, a mode is converted from a normal mode to a BIN mode, a signal at that time is not delayed and is transmitted to a pre-charge section 104 as a BIN control signal BI', and clamp Trs 105A, 105B are turned off. On the other hand, a complementary BIN control signal BIB converting a column signal Y into the BIN mode is transmitted after the delay of a delay circuit 113 in a low signal XW. Accordingly, the signal XW or the signal Y is made later than the Trs 105A, 105B and enters into the BIN mode, and the path of an overcurrent is formed. When a device in the BIN mode is converted into the normal mode, the signal BI is changed from H to L, the complementary BIN control signal BIB is transferred instantaneously without through a delay circuit 114, and the signal XW or Y is altered into the normal mode. On the other hand, the BIN control signal BI' is generated through the circuit 113, and changes the Trs 105A, 105B from the BIN mode to the normal mode.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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title | BURN-IN TEST METHOD FOR SEMICONDUCTOR MEMORY DEVICE AND CONTROL CIRCUIT FOR BURN-IN TIMING FOR IT |
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