JPH0831575B

A semiconductor memory device having a memory cell including a transistor having, as source and drain regions, impurity-diffused regions formed selectively in the active area isolated by field insulating film formed selectively at the surface of a semiconductor substrate and a capacitor comprising a lower electrode including a bottom electrode and a cylindrical electrode. The bottom electrode is formed on an interlayer insulating film formed over the substrate and is connected to one of the impurity-diffused regions through a first hole opened in said interlayer insulating film. The cylindrical electrode is formed at the edge portion of said bottom electrode and a plurality of second holes formed in the interlayer insulating film on said field insulating film. The first hole and the second holes have substantially the same dimensions except for a depth thereof. The second holes are arranged to be a mark representing characters to assist the process control. In addition, a check element fabricated by forming the lower electrodes covering a plurality of second holes and cylindrical electrodes so that these electrodes assume a loop toothed at a certain pitch can be prevented from being broken down even if the dimensions are large.