CIRCUIT AND METHOD FOR MULTIBIT TEST OF SEMICONDUCTOR MEMORYDEVICE

PROBLEM TO BE SOLVED: To shorten the duration of multi-bit tests and to reduce the cost of the tests by enabling a specific bit to be able to be tested separately at the testing time. SOLUTION: A second input circuit section 16 generates internal test selecting signals UPDQ and DWDQ from the output signal of the preceding stage and outputs the signals UPDQ and DWDQ to the succeeding stage. A bit comparing section 18 compares and outputs the data corresponding to normal muti-bit tests when both the signals UPDQ and DWDQ are low. When both the signals UPDQ and DWDQ are high, the section 18 compares D1Di with D1Di and D1Dk with D1D1 and outputs the compared results. A latch section 20 latches the output signals of the section 18 and outputs a signal PICOMi to a bus control section. The bus control section outputs DOI and DOIB at low levels when the signal PICOMj is low. When the signal PICOMi is high and the compared data are the same, the bus control section outputs the same data as the value held by a memory by using the oars.