MULTICHIP MODULE PACKAGE

PROBLEM TO BE SOLVED: To reduce the vertical dimension, that is, the thickness of a multichip module package by a method, wherein a cavity part is provided in a printed- wiring board to arrange efficiently an MCM tile in the cavity part. SOLUTION: A silicon on silicon MCM tile 17, which consists of a silicon substrate 18 and silicon chips 19 and 20, is arranged in a cavity part 16 formed in a PW board 11, which has lower, middle and upper levels 12, 13 and 14. A wire-bonding finger 21 on the substrate 18 is interconnected with a contact pad 23 on the level part 13 of the board 11 via a wire 22. Whereupon, the cavity part 16 is sealed with a structural member. An adaptable capsule-shaped sealing material, which wraps the chips of the tile 17 therein, is made to fill the part 16. Thereby, the thickness of an MC package can be reduced, and a minimization of a system and a device, which adopt the package, becomes possible.