FLIP FLOP CIRCUIT AND SHIFT REGISTER CIRCUIT USING THE CIRCUIT

PURPOSE:To reduce the number of elements constituting a flip flop (FF) circuit and to reduce its area by constituting the FF circuit only of a slave part of a master-slave type circuit and generating a complementary pulse synchronized with transition timing to a prescribed level of a clock signal to drive the FF circuit. CONSTITUTION:An input clock signal CLK is inputted to a 2-input NAND gate 31 in a pulse driver circuit and inputted also to an inverter 32 having a delay function. A delay inverse signal Va outputted from an inverter 32 is inputted to the other input of the NAND gate 31, which generates a reverse phase clock pulse phi2. The pulse 2 is inverted by an inverter 33 and outputted as a positive phase clock pulse phi1. The ON/OFF control of transfer gates 21, 24 in the FF circuit is executed by the pulses phi1, phi2. and after latching input data IN by the gate 21, the data are uutputted from the gate 24. Thereby the same function as the master-slave type can be obtained only by the slave part.