PROCESSING ACCELERATING METHOD FOR INFORMATION PROCESSOR
PURPOSE:To suppress the generation of the overhead of high-order bit decision in the case of cache memory access and to avoid complicated processing when changing the contents of an address map table by separately generating first and second instructions and setting a real address to the second inst...
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| creator | YAMAURA ICHIRO |
| description | PURPOSE:To suppress the generation of the overhead of high-order bit decision in the case of cache memory access and to avoid complicated processing when changing the contents of an address map table by separately generating first and second instructions and setting a real address to the second instruction. CONSTITUTION:A logical address is set to a memory address register 11 by processing a first instruction sequence, and the logical address is translated into the real address by an address map 13 and applied to a memory access processing part 14. The real address is set to a memory address register 12 by processing a second instruction sequence, and the real address is applied to the memory access processing part 14. Therefore, the first instruction for accessing a logical address area with no guarantee to be mapped in a real memory and the second instruction for accessing a logical address area to be surely mapped into the real memory are separately generated, and the logical address area for processing the separated second instruction is secured in the real memory. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH07175663A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH07175663A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH07175663A3</originalsourceid><addsrcrecordid>eNrjZLAICPJ3dg0O9vRzV3B0dnb1cQ1yDAFxfF1DPPxdFNz8gxQ8_YCkL1DY308Bqtw_iIeBNS0xpziVF0pzMyi6uYY4e-imFuTHpxYXJCan5qWWxHsFeBiYG5qbmpkZOxoTowYAkBIpFA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PROCESSING ACCELERATING METHOD FOR INFORMATION PROCESSOR</title><source>esp@cenet</source><creator>YAMAURA ICHIRO</creator><creatorcontrib>YAMAURA ICHIRO</creatorcontrib><description>PURPOSE:To suppress the generation of the overhead of high-order bit decision in the case of cache memory access and to avoid complicated processing when changing the contents of an address map table by separately generating first and second instructions and setting a real address to the second instruction. CONSTITUTION:A logical address is set to a memory address register 11 by processing a first instruction sequence, and the logical address is translated into the real address by an address map 13 and applied to a memory access processing part 14. The real address is set to a memory address register 12 by processing a second instruction sequence, and the real address is applied to the memory access processing part 14. Therefore, the first instruction for accessing a logical address area with no guarantee to be mapped in a real memory and the second instruction for accessing a logical address area to be surely mapped into the real memory are separately generated, and the logical address area for processing the separated second instruction is secured in the real memory.</description><edition>6</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1995</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19950714&DB=EPODOC&CC=JP&NR=H07175663A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19950714&DB=EPODOC&CC=JP&NR=H07175663A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YAMAURA ICHIRO</creatorcontrib><title>PROCESSING ACCELERATING METHOD FOR INFORMATION PROCESSOR</title><description>PURPOSE:To suppress the generation of the overhead of high-order bit decision in the case of cache memory access and to avoid complicated processing when changing the contents of an address map table by separately generating first and second instructions and setting a real address to the second instruction. CONSTITUTION:A logical address is set to a memory address register 11 by processing a first instruction sequence, and the logical address is translated into the real address by an address map 13 and applied to a memory access processing part 14. The real address is set to a memory address register 12 by processing a second instruction sequence, and the real address is applied to the memory access processing part 14. Therefore, the first instruction for accessing a logical address area with no guarantee to be mapped in a real memory and the second instruction for accessing a logical address area to be surely mapped into the real memory are separately generated, and the logical address area for processing the separated second instruction is secured in the real memory.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1995</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAICPJ3dg0O9vRzV3B0dnb1cQ1yDAFxfF1DPPxdFNz8gxQ8_YCkL1DY308Bqtw_iIeBNS0xpziVF0pzMyi6uYY4e-imFuTHpxYXJCan5qWWxHsFeBiYG5qbmpkZOxoTowYAkBIpFA</recordid><startdate>19950714</startdate><enddate>19950714</enddate><creator>YAMAURA ICHIRO</creator><scope>EVB</scope></search><sort><creationdate>19950714</creationdate><title>PROCESSING ACCELERATING METHOD FOR INFORMATION PROCESSOR</title><author>YAMAURA ICHIRO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH07175663A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1995</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>YAMAURA ICHIRO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YAMAURA ICHIRO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PROCESSING ACCELERATING METHOD FOR INFORMATION PROCESSOR</title><date>1995-07-14</date><risdate>1995</risdate><abstract>PURPOSE:To suppress the generation of the overhead of high-order bit decision in the case of cache memory access and to avoid complicated processing when changing the contents of an address map table by separately generating first and second instructions and setting a real address to the second instruction. CONSTITUTION:A logical address is set to a memory address register 11 by processing a first instruction sequence, and the logical address is translated into the real address by an address map 13 and applied to a memory access processing part 14. The real address is set to a memory address register 12 by processing a second instruction sequence, and the real address is applied to the memory access processing part 14. Therefore, the first instruction for accessing a logical address area with no guarantee to be mapped in a real memory and the second instruction for accessing a logical address area to be surely mapped into the real memory are separately generated, and the logical address area for processing the separated second instruction is secured in the real memory.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | PROCESSING ACCELERATING METHOD FOR INFORMATION PROCESSOR |
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