SERIAL SYNCHRONIZATION PROTECTION CIRCUIT FOR PARALLEL DATA
PURPOSE:To accurately count the number of synchronization protection stages in the unit of bits from parallel input data with respect to the serial synchronization protection circuit for parallel data. CONSTITUTION:The protection circuit is made up of an E-OR circuit 11 comparing parallel input data...
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creator | MORIWAKE MASARU DOI KAZUMA |
description | PURPOSE:To accurately count the number of synchronization protection stages in the unit of bits from parallel input data with respect to the serial synchronization protection circuit for parallel data. CONSTITUTION:The protection circuit is made up of an E-OR circuit 11 comparing parallel input data with a PN pattern, a 1st priority encoder 2 outputting valid bit number toward the MSB side from an error bit, a 2nd priority encoder 13 outputting valid bit number toward the LSB side from the error bit, a register 14, an adder circuit 15 adding the valid bit number to the register 14, a selector 16 to allow the register 14 to accumulate the valid bit number when no error bit is in existence and to allow the register 14 to be cleared and to allow the register 14 to accumulate the valid bit number newly, a comparator 17 comparing the added valid bit number with a reference bit number, and an S-R latch FF 18 discriminating it that the protection circuit is synchronized with the parallel input data. |
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CONSTITUTION:The protection circuit is made up of an E-OR circuit 11 comparing parallel input data with a PN pattern, a 1st priority encoder 2 outputting valid bit number toward the MSB side from an error bit, a 2nd priority encoder 13 outputting valid bit number toward the LSB side from the error bit, a register 14, an adder circuit 15 adding the valid bit number to the register 14, a selector 16 to allow the register 14 to accumulate the valid bit number when no error bit is in existence and to allow the register 14 to be cleared and to allow the register 14 to accumulate the valid bit number newly, a comparator 17 comparing the added valid bit number with a reference bit number, and an S-R latch FF 18 discriminating it that the protection circuit is synchronized with the parallel input data.</description><edition>6</edition><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>1995</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19950602&DB=EPODOC&CC=JP&NR=H07143116A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19950602&DB=EPODOC&CC=JP&NR=H07143116A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MORIWAKE MASARU</creatorcontrib><creatorcontrib>DOI KAZUMA</creatorcontrib><title>SERIAL SYNCHRONIZATION PROTECTION CIRCUIT FOR PARALLEL DATA</title><description>PURPOSE:To accurately count the number of synchronization protection stages in the unit of bits from parallel input data with respect to the serial synchronization protection circuit for parallel data. CONSTITUTION:The protection circuit is made up of an E-OR circuit 11 comparing parallel input data with a PN pattern, a 1st priority encoder 2 outputting valid bit number toward the MSB side from an error bit, a 2nd priority encoder 13 outputting valid bit number toward the LSB side from the error bit, a register 14, an adder circuit 15 adding the valid bit number to the register 14, a selector 16 to allow the register 14 to accumulate the valid bit number when no error bit is in existence and to allow the register 14 to be cleared and to allow the register 14 to accumulate the valid bit number newly, a comparator 17 comparing the added valid bit number with a reference bit number, and an S-R latch FF 18 discriminating it that the protection circuit is synchronized with the parallel input data.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1995</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAOdg3ydPRRCI70c_YI8vfzjHIM8fT3UwgI8g9xdQYznT2DnEM9QxTc_IMUAhyDHH18XH0UXBxDHHkYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSbxXgIeBuaGJsaGhmaMxMWoAEzwpzA</recordid><startdate>19950602</startdate><enddate>19950602</enddate><creator>MORIWAKE MASARU</creator><creator>DOI KAZUMA</creator><scope>EVB</scope></search><sort><creationdate>19950602</creationdate><title>SERIAL SYNCHRONIZATION PROTECTION CIRCUIT FOR PARALLEL DATA</title><author>MORIWAKE MASARU ; DOI KAZUMA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH07143116A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1995</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>MORIWAKE MASARU</creatorcontrib><creatorcontrib>DOI KAZUMA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MORIWAKE MASARU</au><au>DOI KAZUMA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SERIAL SYNCHRONIZATION PROTECTION CIRCUIT FOR PARALLEL DATA</title><date>1995-06-02</date><risdate>1995</risdate><abstract>PURPOSE:To accurately count the number of synchronization protection stages in the unit of bits from parallel input data with respect to the serial synchronization protection circuit for parallel data. CONSTITUTION:The protection circuit is made up of an E-OR circuit 11 comparing parallel input data with a PN pattern, a 1st priority encoder 2 outputting valid bit number toward the MSB side from an error bit, a 2nd priority encoder 13 outputting valid bit number toward the LSB side from the error bit, a register 14, an adder circuit 15 adding the valid bit number to the register 14, a selector 16 to allow the register 14 to accumulate the valid bit number when no error bit is in existence and to allow the register 14 to be cleared and to allow the register 14 to accumulate the valid bit number newly, a comparator 17 comparing the added valid bit number with a reference bit number, and an S-R latch FF 18 discriminating it that the protection circuit is synchronized with the parallel input data.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
title | SERIAL SYNCHRONIZATION PROTECTION CIRCUIT FOR PARALLEL DATA |
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