SEMICONDUCTOR MEMORY DEVICE
PURPOSE:To reduce the power source current and peak current at the time of an operation by making a half of plural sense amplifiers operate as N type sense amplifiers and the remainder as P type sense amplifiers. CONSTITUTION:Either of N type sense amplifiers 160 and P type sense amplifiers 270 are...
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creator | SUYAMA JUNICHI SEKINO YOSHIMASA TANAKA YASUHIRO YAMADA HITOSHI UENO JOJI MURASHIMA YOSHIHIRO TOKUNAGA YASUHIRO TANAKA TAKAYUKI SENAGA JIYOU |
description | PURPOSE:To reduce the power source current and peak current at the time of an operation by making a half of plural sense amplifiers operate as N type sense amplifiers and the remainder as P type sense amplifiers. CONSTITUTION:Either of N type sense amplifiers 160 and P type sense amplifiers 270 are placed in operation through latch terminals PL1 and PL2 and the potentials of bit lines BL1, BL2,... in operation are controlled from a 1/2.VCC level to a VCC level or from the 1/2.VCC level to a VSS level; and charging currents of the bit lines BL1, BL2,... in the sense amplifier operation and peak currents at the time of the charging of the bit lines BL1, BL2,... in the sense amplifier operation are reduced to a half. |
format | Patent |
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CONSTITUTION:Either of N type sense amplifiers 160 and P type sense amplifiers 270 are placed in operation through latch terminals PL1 and PL2 and the potentials of bit lines BL1, BL2,... in operation are controlled from a 1/2.VCC level to a VCC level or from the 1/2.VCC level to a VSS level; and charging currents of the bit lines BL1, BL2,... in the sense amplifier operation and peak currents at the time of the charging of the bit lines BL1, BL2,... in the sense amplifier operation are reduced to a half.</description><edition>5</edition><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>1994</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940318&DB=EPODOC&CC=JP&NR=H0676572A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940318&DB=EPODOC&CC=JP&NR=H0676572A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SUYAMA JUNICHI</creatorcontrib><creatorcontrib>SEKINO YOSHIMASA</creatorcontrib><creatorcontrib>TANAKA YASUHIRO</creatorcontrib><creatorcontrib>YAMADA HITOSHI</creatorcontrib><creatorcontrib>UENO JOJI</creatorcontrib><creatorcontrib>MURASHIMA YOSHIHIRO</creatorcontrib><creatorcontrib>TOKUNAGA YASUHIRO</creatorcontrib><creatorcontrib>TANAKA TAKAYUKI</creatorcontrib><creatorcontrib>SENAGA JIYOU</creatorcontrib><title>SEMICONDUCTOR MEMORY DEVICE</title><description>PURPOSE:To reduce the power source current and peak current at the time of an operation by making a half of plural sense amplifiers operate as N type sense amplifiers and the remainder as P type sense amplifiers. CONSTITUTION:Either of N type sense amplifiers 160 and P type sense amplifiers 270 are placed in operation through latch terminals PL1 and PL2 and the potentials of bit lines BL1, BL2,... in operation are controlled from a 1/2.VCC level to a VCC level or from the 1/2.VCC level to a VSS level; and charging currents of the bit lines BL1, BL2,... in the sense amplifier operation and peak currents at the time of the charging of the bit lines BL1, BL2,... in the sense amplifier operation are reduced to a half.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1994</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAOdvX1dPb3cwl1DvEPUvB19fUPilRwcQ3zdHblYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxXgEeBmbmZqbmRo7GRCgBACxBIIw</recordid><startdate>19940318</startdate><enddate>19940318</enddate><creator>SUYAMA JUNICHI</creator><creator>SEKINO YOSHIMASA</creator><creator>TANAKA YASUHIRO</creator><creator>YAMADA HITOSHI</creator><creator>UENO JOJI</creator><creator>MURASHIMA YOSHIHIRO</creator><creator>TOKUNAGA YASUHIRO</creator><creator>TANAKA TAKAYUKI</creator><creator>SENAGA JIYOU</creator><scope>EVB</scope></search><sort><creationdate>19940318</creationdate><title>SEMICONDUCTOR MEMORY DEVICE</title><author>SUYAMA JUNICHI ; SEKINO YOSHIMASA ; TANAKA YASUHIRO ; YAMADA HITOSHI ; UENO JOJI ; MURASHIMA YOSHIHIRO ; TOKUNAGA YASUHIRO ; TANAKA TAKAYUKI ; SENAGA JIYOU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH0676572A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1994</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>SUYAMA JUNICHI</creatorcontrib><creatorcontrib>SEKINO YOSHIMASA</creatorcontrib><creatorcontrib>TANAKA YASUHIRO</creatorcontrib><creatorcontrib>YAMADA HITOSHI</creatorcontrib><creatorcontrib>UENO JOJI</creatorcontrib><creatorcontrib>MURASHIMA YOSHIHIRO</creatorcontrib><creatorcontrib>TOKUNAGA YASUHIRO</creatorcontrib><creatorcontrib>TANAKA TAKAYUKI</creatorcontrib><creatorcontrib>SENAGA JIYOU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SUYAMA JUNICHI</au><au>SEKINO YOSHIMASA</au><au>TANAKA YASUHIRO</au><au>YAMADA HITOSHI</au><au>UENO JOJI</au><au>MURASHIMA YOSHIHIRO</au><au>TOKUNAGA YASUHIRO</au><au>TANAKA TAKAYUKI</au><au>SENAGA JIYOU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR MEMORY DEVICE</title><date>1994-03-18</date><risdate>1994</risdate><abstract>PURPOSE:To reduce the power source current and peak current at the time of an operation by making a half of plural sense amplifiers operate as N type sense amplifiers and the remainder as P type sense amplifiers. CONSTITUTION:Either of N type sense amplifiers 160 and P type sense amplifiers 270 are placed in operation through latch terminals PL1 and PL2 and the potentials of bit lines BL1, BL2,... in operation are controlled from a 1/2.VCC level to a VCC level or from the 1/2.VCC level to a VSS level; and charging currents of the bit lines BL1, BL2,... in the sense amplifier operation and peak currents at the time of the charging of the bit lines BL1, BL2,... in the sense amplifier operation are reduced to a half.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record> |
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subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
title | SEMICONDUCTOR MEMORY DEVICE |
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