COMPUTER-SYSTEM
PURPOSE: To incorporate parallel array processors on a single semiconductor silicon chip. CONSTITUTION: The parallel array processors for large scaled parallel application are formed by low output CMOS provided with a DRAM processing mechanism and processing elements are incorporated on a single chi...
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| creator | MAIKERU CHIYAARUZU DATSUPU JIEEMUZU UOREN DEIIFUENDERUFUAA DONARUDO MAIKERU RESUMAISUTAA ROBAATO RAISUTO RICHIYAADOSON KURAIBU ARAN KORINZU BUINSENTO JIYON SUMOORARU TOMASU NOOMAN BAAKAA BIRII JIYATSUKU NOURUZU RICHIYAADO EDOWAADO NAIYAA DEEBUITSUDO BURUUSU RORUFU RICHIYAADO AANESUTO MAIRUZU |
| description | PURPOSE: To incorporate parallel array processors on a single semiconductor silicon chip. CONSTITUTION: The parallel array processors for large scaled parallel application are formed by low output CMOS provided with a DRAM processing mechanism and processing elements are incorporated on a single chip. The eight processors on the single chip have the processing elements connected to themselves, large scaled memories and input/output mechanisms and they are connected by a corrected topology based on a hypercube. Nodes are connected by a hypercube network topology, a corrected hypercube network topology, a ring network topology or an intra-ring network topology. |
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CONSTITUTION: The parallel array processors for large scaled parallel application are formed by low output CMOS provided with a DRAM processing mechanism and processing elements are incorporated on a single chip. The eight processors on the single chip have the processing elements connected to themselves, large scaled memories and input/output mechanisms and they are connected by a corrected topology based on a hypercube. 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CONSTITUTION: The parallel array processors for large scaled parallel application are formed by low output CMOS provided with a DRAM processing mechanism and processing elements are incorporated on a single chip. The eight processors on the single chip have the processing elements connected to themselves, large scaled memories and input/output mechanisms and they are connected by a corrected topology based on a hypercube. Nodes are connected by a hypercube network topology, a corrected hypercube network topology, a ring network topology or an intra-ring network topology.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | COMPUTER-SYSTEM |
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