ONE-CHIP MICROCOMPUTER
PURPOSE:To suppress a chip area small by performing the operation of a RAM for storing the arithmetic result of a CPU or the like also by a ROM using an electric erase and write enable nonvolatile memory. CONSTITUTION:A flash EEPROM is used for a ROM 20, a read control signal from a CPU 10 is output...
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| creator | INOUE HIROHIKO |
| description | PURPOSE:To suppress a chip area small by performing the operation of a RAM for storing the arithmetic result of a CPU or the like also by a ROM using an electric erase and write enable nonvolatile memory. CONSTITUTION:A flash EEPROM is used for a ROM 20, a read control signal from a CPU 10 is outputted through a control signal line 3c to a control circuit 4c, a read address is outputted to an address bus 1, a series of operations for fetching an instruction from this address of the ROM 20 through a data bus 2 and executing it are repeated, on the other hand, when storing the arithmetic result of the CPU 10, a write control signal and a designating signal for an area to be erased are outputted through a control signal line 3d to a control circuit 4d, the designated area is erased, and the arithmetic result of the CPU 10 is stored. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH06324938A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH06324938A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH06324938A3</originalsourceid><addsrcrecordid>eNrjZBDz93PVdfbwDFDw9XQO8nf29w0IDXEN4mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8V4BHgZmxkYmlsYWjsbEqAEAwxkfgQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ONE-CHIP MICROCOMPUTER</title><source>esp@cenet</source><creator>INOUE HIROHIKO</creator><creatorcontrib>INOUE HIROHIKO</creatorcontrib><description>PURPOSE:To suppress a chip area small by performing the operation of a RAM for storing the arithmetic result of a CPU or the like also by a ROM using an electric erase and write enable nonvolatile memory. CONSTITUTION:A flash EEPROM is used for a ROM 20, a read control signal from a CPU 10 is outputted through a control signal line 3c to a control circuit 4c, a read address is outputted to an address bus 1, a series of operations for fetching an instruction from this address of the ROM 20 through a data bus 2 and executing it are repeated, on the other hand, when storing the arithmetic result of the CPU 10, a write control signal and a designating signal for an area to be erased are outputted through a control signal line 3d to a control circuit 4d, the designated area is erased, and the arithmetic result of the CPU 10 is stored.</description><edition>5</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>1994</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19941125&DB=EPODOC&CC=JP&NR=H06324938A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19941125&DB=EPODOC&CC=JP&NR=H06324938A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>INOUE HIROHIKO</creatorcontrib><title>ONE-CHIP MICROCOMPUTER</title><description>PURPOSE:To suppress a chip area small by performing the operation of a RAM for storing the arithmetic result of a CPU or the like also by a ROM using an electric erase and write enable nonvolatile memory. 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CONSTITUTION:A flash EEPROM is used for a ROM 20, a read control signal from a CPU 10 is outputted through a control signal line 3c to a control circuit 4c, a read address is outputted to an address bus 1, a series of operations for fetching an instruction from this address of the ROM 20 through a data bus 2 and executing it are repeated, on the other hand, when storing the arithmetic result of the CPU 10, a write control signal and a designating signal for an area to be erased are outputted through a control signal line 3d to a control circuit 4d, the designated area is erased, and the arithmetic result of the CPU 10 is stored.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record> |
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| language | eng |
| recordid | cdi_epo_espacenet_JPH06324938A |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
| title | ONE-CHIP MICROCOMPUTER |
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