LOGIC VERIFICATION SYSTEM FOR COMPUTER SYSTEM
PURPOSE:To perform logic verification in environment near to a real machine without manufacturing an experimental model by connecting a reloadable hardware to which a prototype of verification target logic is applied to a real component used in a computer system set as the object of verification via...
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| creator | TADA OSAMU OKAZAKI YOSHINOBU EDAKAWA MITSUGI MORIMOTO KAZUNOBU |
| description | PURPOSE:To perform logic verification in environment near to a real machine without manufacturing an experimental model by connecting a reloadable hardware to which a prototype of verification target logic is applied to a real component used in a computer system set as the object of verification via a component connection part. CONSTITUTION:A logic verification system 1 is provided with a controller 13, a memory device 14, an emulation module 4 that is hardware whose logic can be reloaded, the component connection part 8 which connects the emulation module 4 to the real component, and an internal state recording part 13. When a prescribed switch is turned on and another switch connected to a signal on an emulation moduel 4 side is turned off, the signal on the emulation module side can be connected to the component pin of an adaptor 9a. In such a case, since the component connection part 8 performs processing on all the signals on the emulation module side, the emulation module 4 can be connected to the real component. |
| format | Patent |
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| language | eng |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | LOGIC VERIFICATION SYSTEM FOR COMPUTER SYSTEM |
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