LATCH CIRCUIT

PURPOSE:To simplify a latch circuit by eliminating the need for a switch circuit. CONSTITUTION:Latch circuits D1, D2 which output an L level when a clock signal CK is at an L or H level, fetch and latch input data D in response to the rising or trailing of the clock signal and output the data are em...

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Hauptverfasser:	NANBU HIROAKI, IDEI YOJI, KUSUNOKI TAKESHI, OHATA KENICHI, KANETANI KAZUO
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE
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creator	NANBU HIROAKI IDEI YOJI KUSUNOKI TAKESHI OHATA KENICHI KANETANI KAZUO
description	PURPOSE:To simplify a latch circuit by eliminating the need for a switch circuit. CONSTITUTION:Latch circuits D1, D2 which output an L level when a clock signal CK is at an L or H level, fetch and latch input data D in response to the rising or trailing of the clock signal and output the data are employed for the latch circuits. Then output data from the circuit D1 and output data from the circuit D2 are wired-ORed.
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CONSTITUTION:Latch circuits D1, D2 which output an L level when a clock signal CK is at an L or H level, fetch and latch input data D in response to the rising or trailing of the clock signal and output the data are employed for the latch circuits. Then output data from the circuit D1 and output data from the circuit D2 are wired-ORed.</description><edition>5</edition><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>1994</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940624&DB=EPODOC&CC=JP&NR=H06177717A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19940624&DB=EPODOC&CC=JP&NR=H06177717A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NANBU HIROAKI</creatorcontrib><creatorcontrib>IDEI YOJI</creatorcontrib><creatorcontrib>KUSUNOKI TAKESHI</creatorcontrib><creatorcontrib>OHATA KENICHI</creatorcontrib><creatorcontrib>KANETANI KAZUO</creatorcontrib><title>LATCH CIRCUIT</title><description>PURPOSE:To simplify a latch circuit by eliminating the need for a switch circuit. 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CONSTITUTION:Latch circuits D1, D2 which output an L level when a clock signal CK is at an L or H level, fetch and latch input data D in response to the rising or trailing of the clock signal and output the data are employed for the latch circuits. Then output data from the circuit D1 and output data from the circuit D2 are wired-ORed.</abstract><edition>5</edition><oa>free_for_read</oa></addata></record>
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subjects	BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE
title	LATCH CIRCUIT
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