TRANSFER CONTROL SYSTEM

PURPOSE:To attain high speed data transfer in matching with the processing of a host processor by monitoring a residual number of a processing request to the host processor in a communication circuit at a receiver side and controlling the transfer automatically depending on the number. CONSTITUTION:When the number of processing requests stored in an FIFO circuit 23 reaches a 1st reference value stored in a reference value memory 25, a comparator circuit 24 requests the clock stop to a clock generating circuit 13. Then the clock generating circuit 13 stops the operation of a data transfer circuit 12. Thus, data transfer to a slave communication circuit 2 is stopped and the flowing of the traffic over the processing by the host processor 3 is stopped and the production of overflow of a reception buffer memory 22 is prevented. Furthermore, after the data transfer is stopped, when number of processing requests reaches a 2nd reference value stored in a reference memory 26, a comparator circuit 24 resets clock stop. Thus, the communication from a master communication circuit 1 to a slave communication circuit 2 is restarted.