CELL GENERATOR

PURPOSE:To automatize the layout of different types of basic cells in accordance with know-how to make the generation of a cell pattern efficient by utilizing know-how accumulated by means of manual design. CONSTITUTION:A prescribed layout processing program, a net list as connection information on...

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1. Verfasser:	OE RYOICHI
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES
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creator	OE RYOICHI
description	PURPOSE:To automatize the layout of different types of basic cells in accordance with know-how to make the generation of a cell pattern efficient by utilizing know-how accumulated by means of manual design. CONSTITUTION:A prescribed layout processing program, a net list as connection information on a circuit are stored in a memory 11 and the know-how of manual design such as priority information on wiring and model information on wiring is accumulated in the memory. CPU 10 executes the layout processing program in the memory 11 in accordance with an instruction from a keyboard 12. Namely, automatic wiring is executed based on the net list and automatic wiring is executed in accordance with the arrangement result and know-how information. Manual wiring by an editor is executed as to layout which is not included in know-how. Thus, the layout of the basic cells different in the types is automatized in accordance with the know-how of manual design such as the priority of wiring and the model.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH0573642A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH0573642A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH0573642A3</originalsourceid><addsrcrecordid>eNrjZOBzdvXxUXB39XMNcgzxD-JhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfFeAR4GpubGZiZGjsZEKAEAkKgcsg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CELL GENERATOR</title><source>esp@cenet</source><creator>OE RYOICHI</creator><creatorcontrib>OE RYOICHI</creatorcontrib><description>PURPOSE:To automatize the layout of different types of basic cells in accordance with know-how to make the generation of a cell pattern efficient by utilizing know-how accumulated by means of manual design. CONSTITUTION:A prescribed layout processing program, a net list as connection information on a circuit are stored in a memory 11 and the know-how of manual design such as priority information on wiring and model information on wiring is accumulated in the memory. CPU 10 executes the layout processing program in the memory 11 in accordance with an instruction from a keyboard 12. Namely, automatic wiring is executed based on the net list and automatic wiring is executed in accordance with the arrangement result and know-how information. Manual wiring by an editor is executed as to layout which is not included in know-how. Thus, the layout of the basic cells different in the types is automatized in accordance with the know-how of manual design such as the priority of wiring and the model.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>1993</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19930326&DB=EPODOC&CC=JP&NR=H0573642A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19930326&DB=EPODOC&CC=JP&NR=H0573642A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OE RYOICHI</creatorcontrib><title>CELL GENERATOR</title><description>PURPOSE:To automatize the layout of different types of basic cells in accordance with know-how to make the generation of a cell pattern efficient by utilizing know-how accumulated by means of manual design. CONSTITUTION:A prescribed layout processing program, a net list as connection information on a circuit are stored in a memory 11 and the know-how of manual design such as priority information on wiring and model information on wiring is accumulated in the memory. CPU 10 executes the layout processing program in the memory 11 in accordance with an instruction from a keyboard 12. Namely, automatic wiring is executed based on the net list and automatic wiring is executed in accordance with the arrangement result and know-how information. Manual wiring by an editor is executed as to layout which is not included in know-how. Thus, the layout of the basic cells different in the types is automatized in accordance with the know-how of manual design such as the priority of wiring and the model.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1993</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOBzdvXxUXB39XMNcgzxD-JhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfFeAR4GpubGZiZGjsZEKAEAkKgcsg</recordid><startdate>19930326</startdate><enddate>19930326</enddate><creator>OE RYOICHI</creator><scope>EVB</scope></search><sort><creationdate>19930326</creationdate><title>CELL GENERATOR</title><author>OE RYOICHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH0573642A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1993</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>OE RYOICHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OE RYOICHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CELL GENERATOR</title><date>1993-03-26</date><risdate>1993</risdate><abstract>PURPOSE:To automatize the layout of different types of basic cells in accordance with know-how to make the generation of a cell pattern efficient by utilizing know-how accumulated by means of manual design. CONSTITUTION:A prescribed layout processing program, a net list as connection information on a circuit are stored in a memory 11 and the know-how of manual design such as priority information on wiring and model information on wiring is accumulated in the memory. CPU 10 executes the layout processing program in the memory 11 in accordance with an instruction from a keyboard 12. Namely, automatic wiring is executed based on the net list and automatic wiring is executed in accordance with the arrangement result and know-how information. Manual wiring by an editor is executed as to layout which is not included in know-how. Thus, the layout of the basic cells different in the types is automatized in accordance with the know-how of manual design such as the priority of wiring and the model.</abstract><oa>free_for_read</oa></addata></record>
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subjects	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES
title	CELL GENERATOR
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T17%3A21%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=OE%20RYOICHI&rft.date=1993-03-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPH0573642A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true