SEMICONDUCTOR DEVICE
PURPOSE:To restrain the deterioration in the reliability upon a semiconductor device during the circuit substrate packaging step while enhancing the heat dissipation effect in operation time for improving the productivity in relation to the semiconductor device using a semiconductor chip mounting su...
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creator | HIRAIWA KATSURO KANWA MASARU ASADA KENJI |
description | PURPOSE:To restrain the deterioration in the reliability upon a semiconductor device during the circuit substrate packaging step while enhancing the heat dissipation effect in operation time for improving the productivity in relation to the semiconductor device using a semiconductor chip mounting substrate. CONSTITUTION:After wire-connecting the connection electrode of a semiconductor chip mounted on the stage 11a of a chip mounting substrate to the corresponding inner lead part on the mounting substrate, at least the stage 11a on one surface and a multitude of wiring patterns 11b whose one end is connected to the inner lead part 11b-1 positioned around the stage 11a while the other lead parts 11b-2 are arranged on the other end positioned around the periphery of the substrate are pattern-formed. On the other hand, the rear surface of the substrate is coated with a metallic layer lid while the outer lead parts 11b-2 are bent on the wiring pattern formation surface side in the wiring pattern formation region so that the end sides of the outer lead parts 11b-2 may be aligned on the same surface. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH0547957A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH0547957A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH0547957A3</originalsourceid><addsrcrecordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfFeAR4GpibmlqbmjsZEKAEATyMelA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>HIRAIWA KATSURO ; KANWA MASARU ; ASADA KENJI</creator><creatorcontrib>HIRAIWA KATSURO ; KANWA MASARU ; ASADA KENJI</creatorcontrib><description>PURPOSE:To restrain the deterioration in the reliability upon a semiconductor device during the circuit substrate packaging step while enhancing the heat dissipation effect in operation time for improving the productivity in relation to the semiconductor device using a semiconductor chip mounting substrate. CONSTITUTION:After wire-connecting the connection electrode of a semiconductor chip mounted on the stage 11a of a chip mounting substrate to the corresponding inner lead part on the mounting substrate, at least the stage 11a on one surface and a multitude of wiring patterns 11b whose one end is connected to the inner lead part 11b-1 positioned around the stage 11a while the other lead parts 11b-2 are arranged on the other end positioned around the periphery of the substrate are pattern-formed. On the other hand, the rear surface of the substrate is coated with a metallic layer lid while the outer lead parts 11b-2 are bent on the wiring pattern formation surface side in the wiring pattern formation region so that the end sides of the outer lead parts 11b-2 may be aligned on the same surface.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1993</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19930226&DB=EPODOC&CC=JP&NR=H0547957A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25566,76549</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19930226&DB=EPODOC&CC=JP&NR=H0547957A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HIRAIWA KATSURO</creatorcontrib><creatorcontrib>KANWA MASARU</creatorcontrib><creatorcontrib>ASADA KENJI</creatorcontrib><title>SEMICONDUCTOR DEVICE</title><description>PURPOSE:To restrain the deterioration in the reliability upon a semiconductor device during the circuit substrate packaging step while enhancing the heat dissipation effect in operation time for improving the productivity in relation to the semiconductor device using a semiconductor chip mounting substrate. CONSTITUTION:After wire-connecting the connection electrode of a semiconductor chip mounted on the stage 11a of a chip mounting substrate to the corresponding inner lead part on the mounting substrate, at least the stage 11a on one surface and a multitude of wiring patterns 11b whose one end is connected to the inner lead part 11b-1 positioned around the stage 11a while the other lead parts 11b-2 are arranged on the other end positioned around the periphery of the substrate are pattern-formed. On the other hand, the rear surface of the substrate is coated with a metallic layer lid while the outer lead parts 11b-2 are bent on the wiring pattern formation surface side in the wiring pattern formation region so that the end sides of the outer lead parts 11b-2 may be aligned on the same surface.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1993</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfFeAR4GpibmlqbmjsZEKAEATyMelA</recordid><startdate>19930226</startdate><enddate>19930226</enddate><creator>HIRAIWA KATSURO</creator><creator>KANWA MASARU</creator><creator>ASADA KENJI</creator><scope>EVB</scope></search><sort><creationdate>19930226</creationdate><title>SEMICONDUCTOR DEVICE</title><author>HIRAIWA KATSURO ; KANWA MASARU ; ASADA KENJI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH0547957A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1993</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HIRAIWA KATSURO</creatorcontrib><creatorcontrib>KANWA MASARU</creatorcontrib><creatorcontrib>ASADA KENJI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HIRAIWA KATSURO</au><au>KANWA MASARU</au><au>ASADA KENJI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE</title><date>1993-02-26</date><risdate>1993</risdate><abstract>PURPOSE:To restrain the deterioration in the reliability upon a semiconductor device during the circuit substrate packaging step while enhancing the heat dissipation effect in operation time for improving the productivity in relation to the semiconductor device using a semiconductor chip mounting substrate. CONSTITUTION:After wire-connecting the connection electrode of a semiconductor chip mounted on the stage 11a of a chip mounting substrate to the corresponding inner lead part on the mounting substrate, at least the stage 11a on one surface and a multitude of wiring patterns 11b whose one end is connected to the inner lead part 11b-1 positioned around the stage 11a while the other lead parts 11b-2 are arranged on the other end positioned around the periphery of the substrate are pattern-formed. On the other hand, the rear surface of the substrate is coated with a metallic layer lid while the outer lead parts 11b-2 are bent on the wiring pattern formation surface side in the wiring pattern formation region so that the end sides of the outer lead parts 11b-2 may be aligned on the same surface.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR DEVICE |
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