MANUFACTURE OF SEMICONDUCTOR DEVICE
PURPOSE:To enable a pattern to be sharply lessened in dimensional error so as to obtain a polycrystalline silicon gate element of high accuracy by a method wherein a thin silicon oxide film formed at a low temperature is used as an etching mask. CONSTITUTION:In a method of manufacturing a semiconduc...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | IMAI KAZUO KIMIZUKA MASAKATSU SEKIMOTO MISAO |
| description | PURPOSE:To enable a pattern to be sharply lessened in dimensional error so as to obtain a polycrystalline silicon gate element of high accuracy by a method wherein a thin silicon oxide film formed at a low temperature is used as an etching mask. CONSTITUTION:In a method of manufacturing a semiconductor device, where an amorphous silicon film 53 is deposited on a substrate 51 and then selectively etched using a mask pattern formed on the film 52, and the substrate 51 is thermally treated to turn the amorphous silicon film 53 polycrystalline, a thin silicon oxide film 54 which is formed at a low temperature at which an amorphous silicon film is not turned polycrystalline is used as the mask pattern formed on the amorphous silicon film 53. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH053182A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH053182A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH053182A3</originalsourceid><addsrcrecordid>eNrjZFD2dfQLdXN0DgkNclXwd1MIdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqXmpJfFeAR4GpsaGFkaOxoRVAADkWiIt</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MANUFACTURE OF SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>IMAI KAZUO ; KIMIZUKA MASAKATSU ; SEKIMOTO MISAO</creator><creatorcontrib>IMAI KAZUO ; KIMIZUKA MASAKATSU ; SEKIMOTO MISAO</creatorcontrib><description>PURPOSE:To enable a pattern to be sharply lessened in dimensional error so as to obtain a polycrystalline silicon gate element of high accuracy by a method wherein a thin silicon oxide film formed at a low temperature is used as an etching mask. CONSTITUTION:In a method of manufacturing a semiconductor device, where an amorphous silicon film 53 is deposited on a substrate 51 and then selectively etched using a mask pattern formed on the film 52, and the substrate 51 is thermally treated to turn the amorphous silicon film 53 polycrystalline, a thin silicon oxide film 54 which is formed at a low temperature at which an amorphous silicon film is not turned polycrystalline is used as the mask pattern formed on the amorphous silicon film 53.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1993</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19930108&DB=EPODOC&CC=JP&NR=H053182A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19930108&DB=EPODOC&CC=JP&NR=H053182A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>IMAI KAZUO</creatorcontrib><creatorcontrib>KIMIZUKA MASAKATSU</creatorcontrib><creatorcontrib>SEKIMOTO MISAO</creatorcontrib><title>MANUFACTURE OF SEMICONDUCTOR DEVICE</title><description>PURPOSE:To enable a pattern to be sharply lessened in dimensional error so as to obtain a polycrystalline silicon gate element of high accuracy by a method wherein a thin silicon oxide film formed at a low temperature is used as an etching mask. CONSTITUTION:In a method of manufacturing a semiconductor device, where an amorphous silicon film 53 is deposited on a substrate 51 and then selectively etched using a mask pattern formed on the film 52, and the substrate 51 is thermally treated to turn the amorphous silicon film 53 polycrystalline, a thin silicon oxide film 54 which is formed at a low temperature at which an amorphous silicon film is not turned polycrystalline is used as the mask pattern formed on the amorphous silicon film 53.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1993</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFD2dfQLdXN0DgkNclXwd1MIdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqXmpJfFeAR4GpsaGFkaOxoRVAADkWiIt</recordid><startdate>19930108</startdate><enddate>19930108</enddate><creator>IMAI KAZUO</creator><creator>KIMIZUKA MASAKATSU</creator><creator>SEKIMOTO MISAO</creator><scope>EVB</scope></search><sort><creationdate>19930108</creationdate><title>MANUFACTURE OF SEMICONDUCTOR DEVICE</title><author>IMAI KAZUO ; KIMIZUKA MASAKATSU ; SEKIMOTO MISAO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH053182A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1993</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>IMAI KAZUO</creatorcontrib><creatorcontrib>KIMIZUKA MASAKATSU</creatorcontrib><creatorcontrib>SEKIMOTO MISAO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>IMAI KAZUO</au><au>KIMIZUKA MASAKATSU</au><au>SEKIMOTO MISAO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MANUFACTURE OF SEMICONDUCTOR DEVICE</title><date>1993-01-08</date><risdate>1993</risdate><abstract>PURPOSE:To enable a pattern to be sharply lessened in dimensional error so as to obtain a polycrystalline silicon gate element of high accuracy by a method wherein a thin silicon oxide film formed at a low temperature is used as an etching mask. CONSTITUTION:In a method of manufacturing a semiconductor device, where an amorphous silicon film 53 is deposited on a substrate 51 and then selectively etched using a mask pattern formed on the film 52, and the substrate 51 is thermally treated to turn the amorphous silicon film 53 polycrystalline, a thin silicon oxide film 54 which is formed at a low temperature at which an amorphous silicon film is not turned polycrystalline is used as the mask pattern formed on the amorphous silicon film 53.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_JPH053182A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | MANUFACTURE OF SEMICONDUCTOR DEVICE |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-29T06%3A33%3A02IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=IMAI%20KAZUO&rft.date=1993-01-08&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPH053182A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |