METHOD OF VERIFYING INTEGRATED CIRCUIT MASK PATTERN
PURPOSE:To provide integrated circuit mask pattern verifying method which reduces the burden of network retrieval and that allows accurate comparison. CONSTITUTION:A mask pattern S2 is designed based on a circuit chart S1. Connecting information S4 extracted from the mask pattern is compared with co...
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| creator | JINBO YASUO KANETAKA YUICHI |
| description | PURPOSE:To provide integrated circuit mask pattern verifying method which reduces the burden of network retrieval and that allows accurate comparison. CONSTITUTION:A mask pattern S2 is designed based on a circuit chart S1. Connecting information S4 extracted from the mask pattern is compared with connecting information S5 extracted from the circuit chart for verification. Based on text information, the identification S6 of the bonding wire parts of S4 and S5 is performed and connecting information comparison S13 is performed permitting the identification S6 as a retrieval starting point. Based on signal path tables S7 and S8, the extraction of S9 and S10 of a floating signal path independent from the bonding wire part is performed and the identification 11 of a corresponding gate is carried out. The identified same gates are used as the additional retrieval starting points. |
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CONSTITUTION:A mask pattern S2 is designed based on a circuit chart S1. Connecting information S4 extracted from the mask pattern is compared with connecting information S5 extracted from the circuit chart for verification. Based on text information, the identification S6 of the bonding wire parts of S4 and S5 is performed and connecting information comparison S13 is performed permitting the identification S6 as a retrieval starting point. Based on signal path tables S7 and S8, the extraction of S9 and S10 of a floating signal path independent from the bonding wire part is performed and the identification 11 of a corresponding gate is carried out. The identified same gates are used as the additional retrieval starting points.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>1993</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19930625&DB=EPODOC&CC=JP&NR=H05160262A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19930625&DB=EPODOC&CC=JP&NR=H05160262A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JINBO YASUO</creatorcontrib><creatorcontrib>KANETAKA YUICHI</creatorcontrib><title>METHOD OF VERIFYING INTEGRATED CIRCUIT MASK PATTERN</title><description>PURPOSE:To provide integrated circuit mask pattern verifying method which reduces the burden of network retrieval and that allows accurate comparison. CONSTITUTION:A mask pattern S2 is designed based on a circuit chart S1. Connecting information S4 extracted from the mask pattern is compared with connecting information S5 extracted from the circuit chart for verification. Based on text information, the identification S6 of the bonding wire parts of S4 and S5 is performed and connecting information comparison S13 is performed permitting the identification S6 as a retrieval starting point. Based on signal path tables S7 and S8, the extraction of S9 and S10 of a floating signal path independent from the bonding wire part is performed and the identification 11 of a corresponding gate is carried out. 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CONSTITUTION:A mask pattern S2 is designed based on a circuit chart S1. Connecting information S4 extracted from the mask pattern is compared with connecting information S5 extracted from the circuit chart for verification. Based on text information, the identification S6 of the bonding wire parts of S4 and S5 is performed and connecting information comparison S13 is performed permitting the identification S6 as a retrieval starting point. Based on signal path tables S7 and S8, the extraction of S9 and S10 of a floating signal path independent from the bonding wire part is performed and the identification 11 of a corresponding gate is carried out. The identified same gates are used as the additional retrieval starting points.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES |
| title | METHOD OF VERIFYING INTEGRATED CIRCUIT MASK PATTERN |
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