PACKET COLLECTING CIRCUIT FOR DATA FLOW TYPE SYSTEM

PURPOSE:To provide a packet collecting circuit which can specify the sequence relation of the output packet trains by providing a means to select the packet contents based on a flag. CONSTITUTION:For instance, the caller represented by the flag inputted from an FI is thought to be the second flow pa...

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1. Verfasser: MURAMATSU GOJI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To provide a packet collecting circuit which can specify the sequence relation of the output packet trains by providing a means to select the packet contents based on a flag. CONSTITUTION:For instance, the caller represented by the flag inputted from an FI is thought to be the second flow path. At the same time, a decoder 131 outputs '1' to a permission gate 122. The gate 122 to which a transferable state is shown confirms the permission of transfer given from a transfer control circuit 10N+1 and transmits a transfer permission signal to the corresponding transfer control circuit 102. The circuit 102 gives a transfer request to a collection gate 133 and at the same time the data are fetched by a D latch 112 and outputted. A transfer gate 134 outputs a transfer request to the circuit 10N+1 with the transfer request given from the gate 133. Thus the circuit 10N+1 outputs '0' to a node RN for confirmation of the transfer, and the circuits 100 and 102 receive the output of '0'. Then a selector 132 selects the output of a D latch 112 based on the flag and outputs it to a D latch 11N+1.