LOOP NETWORK CONNECTION SYSTEM

PURPOSE:To connect connected lines altogether and to allow the system not to change the size of the connection part depending on the number of connection lines. CONSTITUTION:The above system is provided with 1st and 2nd branch sections 111, 121 branching a reception signal into two at interconnectio...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: ITSUGAYA KINJI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator ITSUGAYA KINJI
description PURPOSE:To connect connected lines altogether and to allow the system not to change the size of the connection part depending on the number of connection lines. CONSTITUTION:The above system is provided with 1st and 2nd branch sections 111, 121 branching a reception signal into two at interconnection parts of 1st and 2nd loop networks to send a signal comprising frames for time division bit multiplex, 1st and 2nd memories 101,102 storing tentatively one of the branch signals, a 1st insert section 114 inserting a read signal of the 2nd memory 102 to the other branch signal of the 1st branch section 111 and sending the result, a 2nd insert section 124 inserting a read signal of the 1st memory 101 to the other branch signal of the 2nd branch section 121 and sending the result, and 1st and 2nd timing means 112, 113 and 122, 123 detecting respectively timing of a frame from the reception signal at the interconnection part and sending a signal to command the operating timing of the 1st and 2nd branch sections, the 1st and 2nd memories, and the 1st and 2nd insert sections.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH04349734A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH04349734A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH04349734A3</originalsourceid><addsrcrecordid>eNrjZJDz8fcPUPBzDQn3D_JWcPb383N1DvH091MIjgwOcfXlYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxXgEeBibGJpbmxiaOxsSoAQDWjyHk</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>LOOP NETWORK CONNECTION SYSTEM</title><source>esp@cenet</source><creator>ITSUGAYA KINJI</creator><creatorcontrib>ITSUGAYA KINJI</creatorcontrib><description>PURPOSE:To connect connected lines altogether and to allow the system not to change the size of the connection part depending on the number of connection lines. CONSTITUTION:The above system is provided with 1st and 2nd branch sections 111, 121 branching a reception signal into two at interconnection parts of 1st and 2nd loop networks to send a signal comprising frames for time division bit multiplex, 1st and 2nd memories 101,102 storing tentatively one of the branch signals, a 1st insert section 114 inserting a read signal of the 2nd memory 102 to the other branch signal of the 1st branch section 111 and sending the result, a 2nd insert section 124 inserting a read signal of the 1st memory 101 to the other branch signal of the 2nd branch section 121 and sending the result, and 1st and 2nd timing means 112, 113 and 122, 123 detecting respectively timing of a frame from the reception signal at the interconnection part and sending a signal to command the operating timing of the 1st and 2nd branch sections, the 1st and 2nd memories, and the 1st and 2nd insert sections.</description><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>1992</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19921204&amp;DB=EPODOC&amp;CC=JP&amp;NR=H04349734A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19921204&amp;DB=EPODOC&amp;CC=JP&amp;NR=H04349734A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ITSUGAYA KINJI</creatorcontrib><title>LOOP NETWORK CONNECTION SYSTEM</title><description>PURPOSE:To connect connected lines altogether and to allow the system not to change the size of the connection part depending on the number of connection lines. CONSTITUTION:The above system is provided with 1st and 2nd branch sections 111, 121 branching a reception signal into two at interconnection parts of 1st and 2nd loop networks to send a signal comprising frames for time division bit multiplex, 1st and 2nd memories 101,102 storing tentatively one of the branch signals, a 1st insert section 114 inserting a read signal of the 2nd memory 102 to the other branch signal of the 1st branch section 111 and sending the result, a 2nd insert section 124 inserting a read signal of the 1st memory 101 to the other branch signal of the 2nd branch section 121 and sending the result, and 1st and 2nd timing means 112, 113 and 122, 123 detecting respectively timing of a frame from the reception signal at the interconnection part and sending a signal to command the operating timing of the 1st and 2nd branch sections, the 1st and 2nd memories, and the 1st and 2nd insert sections.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1992</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJDz8fcPUPBzDQn3D_JWcPb383N1DvH091MIjgwOcfXlYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxXgEeBibGJpbmxiaOxsSoAQDWjyHk</recordid><startdate>19921204</startdate><enddate>19921204</enddate><creator>ITSUGAYA KINJI</creator><scope>EVB</scope></search><sort><creationdate>19921204</creationdate><title>LOOP NETWORK CONNECTION SYSTEM</title><author>ITSUGAYA KINJI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH04349734A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1992</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>ITSUGAYA KINJI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ITSUGAYA KINJI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>LOOP NETWORK CONNECTION SYSTEM</title><date>1992-12-04</date><risdate>1992</risdate><abstract>PURPOSE:To connect connected lines altogether and to allow the system not to change the size of the connection part depending on the number of connection lines. CONSTITUTION:The above system is provided with 1st and 2nd branch sections 111, 121 branching a reception signal into two at interconnection parts of 1st and 2nd loop networks to send a signal comprising frames for time division bit multiplex, 1st and 2nd memories 101,102 storing tentatively one of the branch signals, a 1st insert section 114 inserting a read signal of the 2nd memory 102 to the other branch signal of the 1st branch section 111 and sending the result, a 2nd insert section 124 inserting a read signal of the 1st memory 101 to the other branch signal of the 2nd branch section 121 and sending the result, and 1st and 2nd timing means 112, 113 and 122, 123 detecting respectively timing of a frame from the reception signal at the interconnection part and sending a signal to command the operating timing of the 1st and 2nd branch sections, the 1st and 2nd memories, and the 1st and 2nd insert sections.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JPH04349734A
source esp@cenet
subjects ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title LOOP NETWORK CONNECTION SYSTEM
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-19T02%3A14%3A36IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=ITSUGAYA%20KINJI&rft.date=1992-12-04&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPH04349734A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true