MULTIPLIER

PURPOSE:To obtain an arithmetic result at a high speed by multiplying a multiplicand by a coefficient, which accords with the state of five high-order bits of a multiplier whose 1st bit below the LSB is 0, and obtaining a partial product. CONSTITUTION:Coefficient output circuits 1 and 2 extract the five high-order bits of the multiplier X while setting the 1st bit below the LSB to 0 and output the coefficient according to the state of the respective bits. Arithmetic circuits 3 and 4 multiply the multiplicand Y by the coefficient to obtain a 1st partial product (XY)1. A coefficient output circuit extracts the five following high-order bits of the multiplicand Y corresponding to the MSB of the extracted five bits and outputs the coefficient according to the state. The arithmetic circuits 3 and 4 multiply the multiplicand by this coefficient to obtain a 2nd partial product (XY)2. Then the partial products XY are added while weighted, so the total number of full-adders (not shown in figure) decreases. Consequently, the circuit scale is reducible and the arithmetic is speeded up.