MEMORY SYSTEM
PURPOSE:To prevent the deterioration of the partial writing performance caused by an ECC memory system and at the same time to prevent the system down due to the occurrence of a parity error in a parity memory system by adding an ECC flag bit and a parity bit to the ECC memory system. CONSTITUTION:A...
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| creator | IMAEDA YASUSHI YASUTO HIROYUKI SUZUKI AKIMASA HAYASHI ITSUKI |
| description | PURPOSE:To prevent the deterioration of the partial writing performance caused by an ECC memory system and at the same time to prevent the system down due to the occurrence of a parity error in a parity memory system by adding an ECC flag bit and a parity bit to the ECC memory system. CONSTITUTION:A memory control part 1 is provided to control the reed/write of a memory together with a part 2 where the information on a main memory are stored. The part l includes an ECC control part 11, a parity control part 12, and an ECC flag control part 13. Meanwhile the part 2 includes a data memory part 21, an ECC flag bit part 22, an ECC bit part 23, and a parity bit part 24. Then the support is secured for both the ECC control and the parity control. Thus the parity bit control is carried out with an ECC flag bit to eliminate the reed-after-write operation in a partial write state. Then the ECC control is executed with the ECC flag bit in a full write state respectively. |
| format | Patent |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | MEMORY SYSTEM |
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