PROCESSOR

PURPOSE:To realize two simply constituted processor functions. CONSTITUTION:The processor is provided with two main sections. These processor's main sections include ALU11A, 11B, registers 12A and 12B, register files 13A and 13B, bus controllers 15A and 15B, instruction decoders 16A and 16B, an...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: NISHIDAI HAJIME
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator NISHIDAI HAJIME
description PURPOSE:To realize two simply constituted processor functions. CONSTITUTION:The processor is provided with two main sections. These processor's main sections include ALU11A, 11B, registers 12A and 12B, register files 13A and 13B, bus controllers 15A and 15B, instruction decoders 16A and 16B, and sequencers 17A and 17B. Through a time division switching circuit 21 that is controlled by a switching control signal A/B provided by a switching control circuit 20, bus controller 15A or 15B of processor's main section A or B accesses memory 22.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH04262450A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH04262450A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH04262450A3</originalsourceid><addsrcrecordid>eNrjZOAMCPJ3dg0O9g_iYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxXgEeBiZGZkYmpgaOxsSoAQBP_hvg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PROCESSOR</title><source>esp@cenet</source><creator>NISHIDAI HAJIME</creator><creatorcontrib>NISHIDAI HAJIME</creatorcontrib><description>PURPOSE:To realize two simply constituted processor functions. CONSTITUTION:The processor is provided with two main sections. These processor's main sections include ALU11A, 11B, registers 12A and 12B, register files 13A and 13B, bus controllers 15A and 15B, instruction decoders 16A and 16B, and sequencers 17A and 17B. Through a time division switching circuit 21 that is controlled by a switching control signal A/B provided by a switching control circuit 20, bus controller 15A or 15B of processor's main section A or B accesses memory 22.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; CONTROL OR REGULATING SYSTEMS IN GENERAL ; CONTROLLING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS ; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS ; PHYSICS ; REGULATING</subject><creationdate>1992</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19920917&amp;DB=EPODOC&amp;CC=JP&amp;NR=H04262450A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19920917&amp;DB=EPODOC&amp;CC=JP&amp;NR=H04262450A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NISHIDAI HAJIME</creatorcontrib><title>PROCESSOR</title><description>PURPOSE:To realize two simply constituted processor functions. CONSTITUTION:The processor is provided with two main sections. These processor's main sections include ALU11A, 11B, registers 12A and 12B, register files 13A and 13B, bus controllers 15A and 15B, instruction decoders 16A and 16B, and sequencers 17A and 17B. Through a time division switching circuit 21 that is controlled by a switching control signal A/B provided by a switching control circuit 20, bus controller 15A or 15B of processor's main section A or B accesses memory 22.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>CONTROL OR REGULATING SYSTEMS IN GENERAL</subject><subject>CONTROLLING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>FUNCTIONAL ELEMENTS OF SUCH SYSTEMS</subject><subject>MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS</subject><subject>PHYSICS</subject><subject>REGULATING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1992</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOAMCPJ3dg0O9g_iYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxXgEeBiZGZkYmpgaOxsSoAQBP_hvg</recordid><startdate>19920917</startdate><enddate>19920917</enddate><creator>NISHIDAI HAJIME</creator><scope>EVB</scope></search><sort><creationdate>19920917</creationdate><title>PROCESSOR</title><author>NISHIDAI HAJIME</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH04262450A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1992</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>CONTROL OR REGULATING SYSTEMS IN GENERAL</topic><topic>CONTROLLING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>FUNCTIONAL ELEMENTS OF SUCH SYSTEMS</topic><topic>MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS</topic><topic>PHYSICS</topic><topic>REGULATING</topic><toplevel>online_resources</toplevel><creatorcontrib>NISHIDAI HAJIME</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NISHIDAI HAJIME</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PROCESSOR</title><date>1992-09-17</date><risdate>1992</risdate><abstract>PURPOSE:To realize two simply constituted processor functions. CONSTITUTION:The processor is provided with two main sections. These processor's main sections include ALU11A, 11B, registers 12A and 12B, register files 13A and 13B, bus controllers 15A and 15B, instruction decoders 16A and 16B, and sequencers 17A and 17B. Through a time division switching circuit 21 that is controlled by a switching control signal A/B provided by a switching control circuit 20, bus controller 15A or 15B of processor's main section A or B accesses memory 22.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JPH04262450A
source esp@cenet
subjects CALCULATING
COMPUTING
CONTROL OR REGULATING SYSTEMS IN GENERAL
CONTROLLING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
FUNCTIONAL ELEMENTS OF SUCH SYSTEMS
MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS
PHYSICS
REGULATING
title PROCESSOR
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-14T02%3A29%3A04IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NISHIDAI%20HAJIME&rft.date=1992-09-17&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPH04262450A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true