INFORMATION PROCESSOR

PURPOSE:To shorten instruction execution time of a central arithmetic processing unit to improve the performance thereof by making the central arithmetic processing unit judge a predicted value for the initial status as the initial status, and by moving control to the execution of the next arithmeti...

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description PURPOSE:To shorten instruction execution time of a central arithmetic processing unit to improve the performance thereof by making the central arithmetic processing unit judge a predicted value for the initial status as the initial status, and by moving control to the execution of the next arithmetic processing instruction. CONSTITUTION:When an input/output processor 2 receives an instruction to start input/output action by a central arithmetic processing unit 1, the processor 2 generates a predicted value for the initial status from adapters 4a-4c that are under the control thereof, and writes the predicted value in main memory 3. Next, the initial status from adapter 4a-4c that are under the control of input/output processor 2 is compared with the written predicted value, and if they match with one another, the processing is continued. Since most of them match with one another, the processing can be forwarded without waiting for the initial status report. If they dot not match, control moves to the abnormality processing. Accordingly, without waiting for the execution of the instruction until returning the initial status from adapters 4a-4c that are under the control of processor 2 the processor 2 can execute the next instruction.
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CONSTITUTION:When an input/output processor 2 receives an instruction to start input/output action by a central arithmetic processing unit 1, the processor 2 generates a predicted value for the initial status from adapters 4a-4c that are under the control thereof, and writes the predicted value in main memory 3. Next, the initial status from adapter 4a-4c that are under the control of input/output processor 2 is compared with the written predicted value, and if they match with one another, the processing is continued. Since most of them match with one another, the processing can be forwarded without waiting for the initial status report. If they dot not match, control moves to the abnormality processing. Accordingly, without waiting for the execution of the instruction until returning the initial status from adapters 4a-4c that are under the control of processor 2 the processor 2 can execute the next instruction.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1992</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19920917&amp;DB=EPODOC&amp;CC=JP&amp;NR=H04262443A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19920917&amp;DB=EPODOC&amp;CC=JP&amp;NR=H04262443A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OKAZAKI MASAMI</creatorcontrib><title>INFORMATION PROCESSOR</title><description>PURPOSE:To shorten instruction execution time of a central arithmetic processing unit to improve the performance thereof by making the central arithmetic processing unit judge a predicted value for the initial status as the initial status, and by moving control to the execution of the next arithmetic processing instruction. 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CONSTITUTION:When an input/output processor 2 receives an instruction to start input/output action by a central arithmetic processing unit 1, the processor 2 generates a predicted value for the initial status from adapters 4a-4c that are under the control thereof, and writes the predicted value in main memory 3. Next, the initial status from adapter 4a-4c that are under the control of input/output processor 2 is compared with the written predicted value, and if they match with one another, the processing is continued. Since most of them match with one another, the processing can be forwarded without waiting for the initial status report. If they dot not match, control moves to the abnormality processing. Accordingly, without waiting for the execution of the instruction until returning the initial status from adapters 4a-4c that are under the control of processor 2 the processor 2 can execute the next instruction.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title INFORMATION PROCESSOR
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