INTERRUPTION CONTROL CIRCUIT
PURPOSE:To enable a processing while changing an interruption generation condition with the use of a software by storing the condition generating the interruption of the software and generating an interruption instruction when the interruption generating condition is satisfied. CONSTITUTION:An inter...
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| creator | SHINOZAKI YOJI |
| description | PURPOSE:To enable a processing while changing an interruption generation condition with the use of a software by storing the condition generating the interruption of the software and generating an interruption instruction when the interruption generating condition is satisfied. CONSTITUTION:An interruption instruction generation part 20 detects an interruption generation condition storing instruction from a microprocessor 6 based on the state of a control bus 2 and an address bus 3, and fetches the interruption generation condition information from a data bus 4. Then, an interruption generation condition storage part 10 stores them through an internal control bus 21. They are outputted to a normal interruption instruction generating part 20 through an interruption generating condition information bus 11, compared with the state of buses 2, 3, and 4. When the establishment of the interruption generating condition is confirmed as a result of the comparison, the interruption instruction generating part 20 interrupts the data bus 4 on a microprocessor 6 side and a data bus 5 on a peripheral circuit 7 side. The software interruption instruction is issued according to the interruption instruction information, and the corresponding interruption processing is executed. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH04230533A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH04230533A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH04230533A3</originalsourceid><addsrcrecordid>eNrjZJDx9AtxDQoKDQjx9PdTcPb3Cwny91Fw9gxyDvUM4WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8V4BHgYmRsYGpsbGjsbEqAEAnvIhVA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>INTERRUPTION CONTROL CIRCUIT</title><source>esp@cenet</source><creator>SHINOZAKI YOJI</creator><creatorcontrib>SHINOZAKI YOJI</creatorcontrib><description>PURPOSE:To enable a processing while changing an interruption generation condition with the use of a software by storing the condition generating the interruption of the software and generating an interruption instruction when the interruption generating condition is satisfied. CONSTITUTION:An interruption instruction generation part 20 detects an interruption generation condition storing instruction from a microprocessor 6 based on the state of a control bus 2 and an address bus 3, and fetches the interruption generation condition information from a data bus 4. Then, an interruption generation condition storage part 10 stores them through an internal control bus 21. They are outputted to a normal interruption instruction generating part 20 through an interruption generating condition information bus 11, compared with the state of buses 2, 3, and 4. When the establishment of the interruption generating condition is confirmed as a result of the comparison, the interruption instruction generating part 20 interrupts the data bus 4 on a microprocessor 6 side and a data bus 5 on a peripheral circuit 7 side. The software interruption instruction is issued according to the interruption instruction information, and the corresponding interruption processing is executed.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1992</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19920819&DB=EPODOC&CC=JP&NR=H04230533A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19920819&DB=EPODOC&CC=JP&NR=H04230533A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHINOZAKI YOJI</creatorcontrib><title>INTERRUPTION CONTROL CIRCUIT</title><description>PURPOSE:To enable a processing while changing an interruption generation condition with the use of a software by storing the condition generating the interruption of the software and generating an interruption instruction when the interruption generating condition is satisfied. CONSTITUTION:An interruption instruction generation part 20 detects an interruption generation condition storing instruction from a microprocessor 6 based on the state of a control bus 2 and an address bus 3, and fetches the interruption generation condition information from a data bus 4. Then, an interruption generation condition storage part 10 stores them through an internal control bus 21. They are outputted to a normal interruption instruction generating part 20 through an interruption generating condition information bus 11, compared with the state of buses 2, 3, and 4. When the establishment of the interruption generating condition is confirmed as a result of the comparison, the interruption instruction generating part 20 interrupts the data bus 4 on a microprocessor 6 side and a data bus 5 on a peripheral circuit 7 side. The software interruption instruction is issued according to the interruption instruction information, and the corresponding interruption processing is executed.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1992</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJDx9AtxDQoKDQjx9PdTcPb3Cwny91Fw9gxyDvUM4WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8V4BHgYmRsYGpsbGjsbEqAEAnvIhVA</recordid><startdate>19920819</startdate><enddate>19920819</enddate><creator>SHINOZAKI YOJI</creator><scope>EVB</scope></search><sort><creationdate>19920819</creationdate><title>INTERRUPTION CONTROL CIRCUIT</title><author>SHINOZAKI YOJI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH04230533A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1992</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SHINOZAKI YOJI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHINOZAKI YOJI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INTERRUPTION CONTROL CIRCUIT</title><date>1992-08-19</date><risdate>1992</risdate><abstract>PURPOSE:To enable a processing while changing an interruption generation condition with the use of a software by storing the condition generating the interruption of the software and generating an interruption instruction when the interruption generating condition is satisfied. CONSTITUTION:An interruption instruction generation part 20 detects an interruption generation condition storing instruction from a microprocessor 6 based on the state of a control bus 2 and an address bus 3, and fetches the interruption generation condition information from a data bus 4. Then, an interruption generation condition storage part 10 stores them through an internal control bus 21. They are outputted to a normal interruption instruction generating part 20 through an interruption generating condition information bus 11, compared with the state of buses 2, 3, and 4. When the establishment of the interruption generating condition is confirmed as a result of the comparison, the interruption instruction generating part 20 interrupts the data bus 4 on a microprocessor 6 side and a data bus 5 on a peripheral circuit 7 side. The software interruption instruction is issued according to the interruption instruction information, and the corresponding interruption processing is executed.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | INTERRUPTION CONTROL CIRCUIT |
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